• Title/Summary/Keyword: 2D Scaling

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A Study on Brand Image Preference and Fashion Advertising Strategy (상표이미지 선호도와 패션 광고 전략에 관한 연구 - 여대생을 중심으로 -)

  • Kim Moon Jin;Rim Sook Ja
    • Journal of the Korean Society of Clothing and Textiles
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    • v.13 no.3 s.31
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    • pp.197-206
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    • 1989
  • This study was to investigate brand images of ladies wear and the effects of fashion advertisements, and to determine the difference of brand image preference and the effects of fashion advertising by clothing life style. 421 subjects were gathered through stratified sampling method and, for data analysis, frequency distribution, $x^2-test$, Cronbach'$\alpha$, ANOVA, Duncan's multiple Range test, Multiple Dimentional Scaling (M.D.S.), Factor analysis, Cluster analysis, were conducted. The results are as follows; 1. In image formation process, feminine as formal image, manish as casual image, were recognized. 2. Four factors were determined for analysis of clothing life styles and with these factors five different clothing life style groups were classified. 3. There was a meaningful difference between clothing life style and brand image preference, and also between clothing life style and the effects of fashion advertisement. From these findings, general and specific fashion advertising strategies are proposed.

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A Design of CMOS ADC for Video Interface (비디오 신호 인터페이스를 위한 CMOS ADC의 설계)

  • 안승헌;권오준;임진업;최중호
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.975-978
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    • 2003
  • 본 논문에서는 비디오 신호 인터페이스를 위해 10비트 50MHz ADC 를 설계하였으며 DCL(digital-error correction logic)을 갖는 3-3-3-4 구조의 파이프라인 방식을 사용하였다. SHA(sample and hold amplifier)와 MDAC (multiplying digital-to-analog converter)에 쓰이는 증폭기는 높은 이득을 갖도록 gain-boosting 기법을 적용하였으며, 전력소모와 면적을 줄이기 위해 capacitor scaling 기법을 적용하였다. 본 ADC 는 0.35 μm double-poly four-metal n-well CMOS 공정으로 설계 및 제작하였으며, 전체 회로는 3.3V 단일 전원 전압에서 동작하도록 설계하였다. 측정 결과 5MHz 의 입력을 인가하였을 때 SNDR 은 56.7dB, 전체 전력 소모는 112mW 이며, 입출력 단의 패드를 포함한 전체 칩 면적은 2.6mm×2.6mm이다.

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A New Method for Color Feature Representation of Color Image in Content-Based Image Retrieval Projection Maps

  • Kim, Won-Ill
    • Journal of The Institute of Information and Telecommunication Facilities Engineering
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    • v.9 no.2
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    • pp.73-79
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    • 2010
  • The most popular technique for image retrieval in a heterogeneous collection of color images is the comparison of images based on their color histogram. The color histogram describes the distribution of colors in the color space of a color image. In the most image retrieval systems, the color histogram is used to compute similarities between the query image and all the images in a database. But, small changes in the resolution, scaling, and illumination may cause important modifications of the color histogram, and so two color images may be considered to be very different from each other even though they have completely related semantics. A new method of color feature representation based on the 3-dimensional RGB color map is proposed to improve the defects of the color histogram. The proposed method is based on the three 2-dimensional projection map evaluated by projecting the RGB color space on the RG, GB, and BR surfaces. The experimental results reveal that the proposed is less sensitive to small changes in the scene and that achieve higher retrieval performances than the traditional color histogram.

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Flow-induced interior noise from a turbulent boundary layer of a towed body

  • Abshagen, J.;Kuter, D.;Nejedl, V.
    • Advances in aircraft and spacecraft science
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    • v.3 no.3
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    • pp.259-269
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    • 2016
  • In this work results from an underwater experiment on flow-induced noise in the interior of a towed body generated from a surrounding turbulent boundary layer are presented. The measurements were performed with a towed body under open sea conditions at towing depths below 100 m and towing speeds ranging from 2.4 m/s to 6.2 m/s (4 kn to 12 kn). Focus is given in the experiments to the relation between (outer) wall pressure fluctuations and the (inner) hydroacoustic near-field on the reverse side of a flat plate. The plate configuration consists of a sandwich structure with an (thick) outer polyurethane layer supported by an inner thin layer from fibre-reinforced plastics. Parameters of the turbulent boundary layer are estimated in order to analyse scaling relations of wall-pressure fluctuations, interior hydroacoustic noise, and the reduction of pressure fluctuations through the plate.

ACCURACY ASSESSMENT BY REFINING THE RATIONAL POLYNOMIALS COEFFICIENTS(RPCs) OF IKONOS IMAGERY

  • LEE SEUNG-CHAN;JUNG HYUNG-SUP;WON JOONG-SUN
    • Proceedings of the KSRS Conference
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    • 2004.10a
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    • pp.344-346
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    • 2004
  • IKONOS 1m satellite imagery is particularly well suited for 3-D feature extraction and 1 :5,000 scale topographic mapping. Because the image line and sample calculated by given RPCs have the error of more than 11m, in order to be able to perform feature extraction and topographic mapping, rational polynomial coefficients(RPCs) camera model that are derived from the very complex IKONOS sensor model to describe the object-image geometry must be refined by several Ground Control Points(GCPs). This paper presents a quantitative evaluation of the geometric accuracy that can be achieved with IKONOS imagery by refining the offset and scaling factors of RPCs using several GCPs. If only two GCPs are available, the offsets and scale factors of image line and sample are updated. If we have more than three GCPs, four parameters of the offsets and scale factors of image line and sample are refined first, and then six parameters of the offsets and scale factors of latitude, longitude and height are updated. The stereo images acquired by IKONOS satellite are tested using six ground points. First, the RPCs model was refined using 2 GCPs and 4 check points acquired by GPS. The results from IKONOS stereo images are reported and these show that the RMSE of check point acquired from left images and right are 1.021m and 1.447m. And then we update the RPCs model using 4 GCPs and 2 check points. The RMSE of geometric accuracy is 0.621 m in left image and 0.816m in right image.

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A Study on the Resistance Against Environmental Loading of the Fine-Size Exposed Aggregate Portland Cement Concrete Pavements (소입경 골재노출콘크리트포장의 환경하중 저항성에 대한 연구)

  • Chon, Beom-Jun;Lee, Seung-Woo;Chae, Sung-Wook;Bae, Jae-Min
    • International Journal of Highway Engineering
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    • v.11 no.2
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    • pp.99-109
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    • 2009
  • Fine-size exposed aggregate portland cement concrete pavements (FEACP) have surface texture of exposed aggregate by removing upper 2$\sim$3mm mortar of surface of which curing is delayed by using delay-setting agent. FEACPs have advantages of maintaining low-noise and adequate skid-resistance level during the performance period than general portland cement concrete pavements. It is necessary to ensure the durability environmental loading to prevent unexpected distress during the service life of FEACP. In the process of curing, volume change accompanied change in by moisture and temperature could be an important cause of crack in concrete to construct for successful FEACP, The use of chloride containing deicer may accelerate defects of concrete pavement, such as crack and scaling. This study aim to evaluate environmental loading resistance of FEACP, based on the estimation of shrinkage-crack-control-capability by moisture evaporation and scaling by deicer in freeze-thaw reaction.

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A 14b 150MS/s 140mW $2.0mm^2$ 0.13um CMOS ADC for SDR (Software Defined Radio 시스템을 위한 14비트 150MS/s 140mW $2.0mm^2$ 0.13um CMOS A/D 변환기)

  • Yoo, Pil-Seon;Kim, Cha-Dong;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.27-35
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    • 2008
  • This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

Transient Simulations of Concrete Ablation due to a Release of Molten Core Material (방출된 노심용융 물질에 의한 콘크리트 침식 천이 모의)

  • Kim, H.Y.;Park, J.H.;Kim, H.D.;Kim, S.W.
    • Proceedings of the KSME Conference
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    • 2007.05b
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    • pp.3491-3496
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    • 2007
  • If a molten core is released from a reactor vessel into a reactor cavity during a severe accident, an important safety issue of coolability of the molten core from top-flooding and concrete ablation due to a molten core concrete interaction (MCCI) is still unresolved. The released molten core debris would attack the concrete wall and basemat of the reactor cavity, which will lead to inevitable concrete decompositions and possible radiological releases. In a OECD/MCCI project scheduled for 4 years from 2002. 1 to 2005. 12, a series of tests were performed to secure the data for cooling the molten core spread out at the reactor cavity and for the 2-D long-term core concrete interaction (CCI). The tests included not only separate effect tests such as a melt eruption, water ingression, and crust failure tests with a prototypic material but also 2-D CCI tests with a prototypic material under dry and flooded cavity conditions. The paper deals with the transient simulations on the CCI-2 test by using a severe accident analysis code, CORQUENCH, which was developed at Argonne National Laboratory (ANL). Similar simulations had been already per for me d by using MELCOR 1.8.5 code. Unlike the MELCOR 1.8.5, the CORQUENCH includes a melt eruption mode I and a newly developed water ingression model based on the water ingression tests under the OECD/MCCI project. In order to adjust the geometrical differences between the CCI-2 test (rectangular geometry) and the simulations (cylindrical geometry), the same scaling methodology as used in the MELCOR simulation was applied. For the direct comparison of the simulation results, the same inputs for the MELCOR simulation were used. The simulation results were compared with the previous results by using MELCOR 1.8.5.

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Image Compression using the Multiwavelet Filter Bank of EZW Structure (EZW 구조의 멀티웨이브릿 필터뱅크를 이용한 영상압축)

  • 권기창;권기룡;권영담
    • Journal of Korea Multimedia Society
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    • v.6 no.1
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    • pp.58-66
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    • 2003
  • In this paper. an image compression of embedded zerotree structure using multiwavelet filter banks is proposed. Multiwavelet is used DGHM(Donovan, Geronimo, Hardin, and Massopust) scaling functions and wavelet functions of a new method with two channel fillet banks. The important properties of the DGHM multiwavelet are orthogonality and approximation order. The DCHM muitiwavelet using the this paper preserves the approximation order=2 for better energy compaction and perfect reconstruction. Image compression using the preposed DGHM multiwavelet is better PSNR for compression ratio than single Daubechies wavelet(D4), Biorthogoanl wavelet, and GHM(Geronimo, Hardin, and Massopust) multi wavelet.

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Design of PCA Architecture Based on Quantum-Dot Cellular Automata (QCA 기반의 효율적인 PCA 구조 설계)

  • Shin, Sang-Ho;Lee, Gil-Je;Yoo, Kee-Young
    • Journal of Advanced Navigation Technology
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    • v.18 no.2
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    • pp.178-184
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    • 2014
  • CMOS technology based on PCA is very efficient at an implementation of memory or ALU. However, there has been a growing interest in quantum-dot cellular automata (QCA) because of the limitation of CMOS scaling. In this paper, we propose a design of PCA architecture based on QCA. In the proposed PCA design, we utilize D flip-flop and XOR logic gate without wire crossing technique, and design a input and rule control switches. In experiment, we perform the simulation of the proposed PCA architecture by QCADesigner. As the result, we confirm the efficiency the proposed architecture.