• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.2
• /
• pp.295-301
• /
• 2012

In this article, we have designed SHA, which has 12 Bit resolution at an input signal range of 1 $V_{pp}$ and operates at a sampling speed of 100 MS/s in order to use at front of high speed ADC. SFDR(Spurious Free Dynamic Range) of the proposed system drops to approximately 66.3 dB resolution when the input frequency is 5 MHz, and the sampling frequency is 100 MHz, however, the circuit without a feedthrough has 12 bit resolution with approximately 73 dB.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.8
• /
• pp.10-21
• /
• 1999

This paper describes a 12bit CMOS current cell matrix D/A converter which shows a conversion rate of 65MHz and a power supply of 3.3V. Designed D/A converter utilizes current cell matrix structure with good monotonicity characteristic and fast settling time, and it is implemented by using the tree structure bias circuit, the symmetrical routing method with ground line and the cascode current switch to reduce the errors of the conventional D/A converter caused by a threshold voltage mismatch of current cells and a voltage drop of the ground line. The designed D/A converter was implemented with a $0.6{\mu}m$ CMOS n-well technology. The measured data shows a settling time of 20ns, a conversion rate of 50 MHz and a power dissipation of 35.6mW with a single power supply of 3.3V. The experimental SNR, DNL, and INL of the D/A converter is measured to be 55dB, ${\pm}0.5LSB$, and ${\pm}2LSB$, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.4
• /
• pp.211-216
• /
• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.7 s.361
• /
• pp.7-11
• /
• 2007

This paper presents a multiband octa-phase LC VCO for SDR receiver. Four identical LC VCOs are connected by using series coupling transistor to obtain the octa-phase signal and low phase noise characteristic. For a multiband application, a band tuning circuit that consists of a switch capacitor circuit and two MOS varactors is proposed. As the MOS switch is on/off state, the frequency range will be varied. In addition, two varactors make the VCO be immune to process variation of the oscillation frequency. The VCO is designed in 0.18-um CMOS technology, consumes 12mA current from 1.8V supply voltage and operates with a frequency band from 885MHz to 1.342GHz (41% tuning range). As driving sub-harmonic mixer, the proposed VCO covers 3 standards(CDMA 2000 1x, WCDMA, WiBro). The measured phase noise is -105dBc@100kHz, -115dBc@1MHz, -130dBc@10MHz for CDMA 2000 1x, WCDMA, WiBro respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.3
• /
• pp.193-197
• /
• 2013

This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

• Current Optics and Photonics
• /
• v.2 no.1
• /
• pp.34-38
• /
• 2018

An X-band microwave photonic (MWP) filter using switch-based fiber-optic delay lines has been proposed and experimentally demonstrated. It is composed of two electro-optic modulators (EOMs) and $2{\times}2$ optical MEMS-switch-based fiber-optic delay lines. By changing time-delay difference and coefficients of each wavelength signal by using fiber-optic delay lines and an electro-optic modulator, respectively, a bandpass filter or a notch filter can be implemented. For an X-band MWP filter with four channel elements, fiber-optic delay lines with the unit time-delay of 50 ps have been experimentally realized and the frequency responses corresponding to the time-delays has been measured. The measured frequency response error at center frequency and the time-delay difference error were 180 MHz at 10 GHz and 3.2 ps, respectively, when the fiber-optic delay line has the time-delay difference of 50 ps.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.13 no.11
• /
• pp.5447-5451
• /
• 2012

This paper presents a pattern-switchable microstrip patch antenna with loop structure. The loop structure for switchable radiation beam pattern is connected with feeding line of the microstrip patch antenna. As changing switch on/off state, the radiation beam pattern can be changed. The target frequency is 2.4 GHz and maximum radiation gain is 3.2dBi. The proposed antenna is useful for diversity antenna and smart antenna in modern wireless communication including MIMO (Multi-Input Multi-Output) and WLAN system. The sizes of the rectangular patch and the ground plane are $28mm{\times}28mm$ and $40mm{\times}50mm$, respectively. The simulation and experimental results show that the antenna radiation pattern can be changed with switch on/off configuration.

• ETRI Journal
• /
• v.41 no.4
• /
• pp.536-548
• /
• 2019

In this study, an electronically steerable parasitic array radiator (ESPAR) antenna via analog radio frequency (RF) switches for a single RF chain MIMO system is presented. The proposed antenna elements are spaced at ${\lambda}/64$, and the antenna size is miniaturized via a dielectric radome. The optimum reactance load value is calculated via the beamforming load search algorithm. A switch simplifies the design and implementation of the reactance loads and does not require additional complex antenna matching circuits. The measured impedance bandwidth of the proposed ESPAR antenna is 1,500 MHz (1.75 GHz-3.25 GHz). The proposed antenna exhibits a beam pattern that is reconfigurable at 2.48 GHz due to changes in the reactance value, and the measured peak antenna gain is 4.8 dBi. The reception performance is measured by using a $4{\times}4$ BPSK signal. The measured average SNR is 17 dB when using the proposed ESPAR antenna as a transmitter, and the average SNR is 16.7 dB when using a four-conventional monopole antenna.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.5
• /
• pp.1073-1081
• /
• 2005

This paper describes a 3.3 V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method. Most of Dfh converters with hiか speed current drive are an architecture choosing current switch cell, column, row decoding method but this decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. The designed D/A converter with an active chip area of $0.953\;mm^2$ is fabricated by using a 0.35um process. The simulation data shows that the rise/fall time, settling time, and INL/DNL are 1.92/2.1 ns, 12.71 ns, and a less than ${\pm}2.3/{\pm}58$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3 V is about 224 mW.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.62 no.6
• /
• pp.792-797
• /
• 2013

In a indoor microwave power distribution system, matching-type power dividing switch is proposed and designed with a various power dividing ratio. A matching coaxial cable probe is used behind the output probe for the reflecting power absorption. Reflecting characteristics of the matching coaxial cable probe are calculated by analyzing the S-parameter of this structure. Newly proposed matching-type switch shows a very low return loss less than -30dB at the operating frequency of 2.45GHz with a dividing power ratio of 50.2%. The simulated results by use of 3-stage power divider shows a good agreement with the theoretical estimation for the various combination of the different switching ratio.