• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.36-42
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• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.659-662
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• 2005

A parameterized FFT/IFFT core generator (PFFT_CoreGen) is designed, which can be used as an essential IP (Intellectual Property) in various OFDM modem designs. The PFFT_CoreGen generates Verilog-HDL models of FFT cores in the range of 64 ${\sim}$ 2048-point. To optimize the performance of the generated FFT cores, the PFFT_CoreGen can select the word-length of input data, internal data and twiddle factors in the range of 8-b ${\sim}$ 24-b. Some design techniques for low-power design are considered from algorithm level to circuit level.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.372-381
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• 2014

This study examined a radar signal active cancelation technique, which is a theoretical way of achieving stealth by employing a baseband process that involves sampling the incoming hostile radar signal, analyzing its characteristics, and generating countermeasure signals to cancel out the linear-FM signal of the hostile radar signal reflected from the airborne target. To successfully perform an active cancelation, the effects of errors in the countermeasure signal were first analyzed. To generate the countermeasure signal that requires very fast and accurate processing, the down-sampling technique with the suboptimal maximum likelihood estimation (sMLE) scheme was proposed to improve the speed of the estimation process while preserving the estimation accuracy. The simulation results showed that the proposed down-sampling technique using a 2048 FFT size yields substantial power reduction despite its small FFT size and exhibits similar performance to the sMLE scheme using the 32768 FFT size.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.39 no.3
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• pp.53-61
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• 2002

In this paper, the authors proposed the digital audio watermarking algorithm for a high quality audio. Today, the digital watermark is used to confirm to the digital copyright protection, not only the digital image but the digital audio study is an activeness in the digital watermarking area. Especially, the watermark insertion in the digital audio area affects deeply not only a robustness but the audio quality of the watermarked audio data. Generally, the audio watermark is inserted in the frequence domain after FFT, the quality of audio data is affected by the watermark insertion. Thus, a high quality audio to be maintained at the same time, the study related a inserting of the robustness watermark happened to a hot issue. In this paper, the authors proposed the digital audio watermarking algorithm using psychoacoustic model and MDCT/IMDCT (Modified Discrete Cosine Transform/Inverse Modified Discrete Cosine Transform). In the proposed scheme, the authors experimented the stereo audio file with 44.1KHz, and 128kbps for the audio watermarking algorithm proposed. When the audio data is processed by MDCT, the watermark is able to insert into the frequence domain with 256, 1024 and 2048 interval. In case of 50㎳ RMS window, it was confirmed that the difference between the original audio data and the watermarked audio data of RMS power is 0.8㏈.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.114-121
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• 2005

In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1709-1716
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• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.2
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• pp.33-41
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• 2001

Currently, the compression is one of the most important technology in multimedia society. Audio files arc rapidly propagated throughout internet Among them, the most famous one is MP-3(MPEC-1 Laver3) which can obtain CD tone from 128Kbps, but tone quality is abruptly down below 64Kbps. MPEC-II AAC(Advanccd Audio Coding) is not compatible with MPEG 1, but it has high compression of 1.4 times than MP 3, has max. 7.1 and 96KHz sampling rate. In this paper, we propose an algorithm that decreased the capacity of AAC encoding computation but increased the processing speed by optimizing psychoacoustic model which has enormous amount of computation in MPEG 2 AAC encoder. The optimized psychoacoustic model algorithm was implemented by C++ language. The experiment shows that the psychoacoustic model carries out FFT(Fast Fourier Transform) computation of 3048 point with 44.1 KHz sampling rate for SMR(Signal to Masking Ratio), and each entropy value is inputted to the subband filters for the control of encoder block. The proposed psychoacoustic model is operated with high speed because of optimization of unpredictable value. Also, when we transform unpredictable value into a tonality index, the speed of operation process is increased by a tonality index optimized in high frequency range.