• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.517-521
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• 2018

In this paper, we designed a microstrip antenna for LTE / WLAN for wireless mobile communication high - speed communication network. The substrate of the proposed antenna is FR-4 (er = 4.3), the size is $20[mm]{\times}40[mm]$ and can be used in the frequency band of 2.77 [GHz] and 5 [GHz] Respectively. The simulation was performed using CST Microwave Studio 2014. The simulation result shows that the gain is 2.034 [dBi] at 2.77 [GHz] and 4.95 [dBi] at 5 [GHz]. The S-parameter was also found to be less than -10 [dB] (WSWR 2: 1) in the desired frequency band. The frequency bands of LTE and WLAN are widely used around the world, and the usage of the frequency is also increasing. For this reason, the dual-band antenna of LTE / WLAN is designed to help many users in a good way to use both technologies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1021-1029
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• 2006

In this paper, we designed and implemented a dual wideband dipole type antenna for the reception of S-DMB (Satellite Digital Multimedia Broadcasting) and 2.4/5 GHz WLAN(Wireless Local Area Network) signals. The proposed antenna based on conventional monopole type dual band antenna was implemented as planar wideband dipole type antenna with the volume of $8{\times}33.8{\times}1.68mm^3$. The proposed antenna is printed type on FR4 substrate of 1.6 mm thick and composed of a dipole type antenna for low frequency band and two symmetric structured resonance elements for high frequency band. We confirmed antenna area with dense surface current for each frequency band with simulation. By varying the length of the antenna area with dense surface current, we could vary resonance frequency of each frequency band separately. Impedance bandwidths$(VSWR{\leq}2)$ are 362 MHz(14.23 %) for 2 GHz band and 1188 MHz(22.13, %) for 5 GHz band which show wideband characteristic. Measured maximum gains were 4.33 dBi for 2 GHz band and 5.48 dBi for 5 GHz band which showed improved performance. And the implemented antenna has a good omni-directional radiation pattern characteristic.

• Journal of Advanced Navigation Technology
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• v.25 no.6
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• pp.530-535
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• 2021

In this paper, the design method for a chipless RFID tag using ELC resonators is proposed. A four-bit chipless RFID tag is designed in a two by two array configuration using three ELC resonators with different resonant peak frequencies and one compact IDC resonator. The resonant peak frequency of the bistatic RCS for the IDC resonator is 3.125 GHz, whereas those of the three ELC resonators are adjusted to be at 4.225 GHz, 4.825 GHz, and 5.240 GHz, respectively, by using the gap between the capacitor-shaped strips in the ELC resonator. The spacing between the resonators is 1 mm. Proposed four-bit tag is fabricated on an RF-301 substrate with dimensions of 50 mm×20 mm and a thickness of 0.8 mm. It is observed from experiment results that the resonant peak frequencies of the fabricated four-bit chipless RFID tag are 3.290 GHz, 4.295 GHz, 4.835 GHz, and 5.230 GHz, respectively, which is similar to the simulation results with errors in the range between -2.3% and 0.2%.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.4
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• pp.549-554
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• 2017

In this paper, we studied the design and fabrication of $2{\times}2$ microstrip array antenna at around 5 GHz band.. To improve of frequency properties of antenna, feed microstrip patch antenna was simulated by HFSS(High Frequency Structure Simulator). A $2{\times}2$ array antenna was designed and fabricated by photolithograph on an FR4 substrate (dielectric constant of 4.4 and thickness of 1.6 mm). The fabricated $2{\times}2$ array antenna showed a center frequency, the minimum return loss and bandwidth were 5.3 GHz, -24dB, and 390MHz, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• Journal of Korea Society of Industrial Information Systems
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• v.23 no.4
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• pp.23-31
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• 2018

This paper presented the implementation and design of the 2T-2R wireless HD video streaming systems over 1.7 GHz frequency band using 3GPP LTE-TDD standard on NI USRP RIO SDR platform. The baseband of the system used USRP RIO that are stored in Xilinx Kintex-7 chip to implement LTE-TDD transceiver modem, the signal that are transmitted from USRP RIO up or down converts to 1.7 GHz by using self-designed 1.7 GHz RF transceiver modules and it is finally communicated HD video data through self-designed 2x9 sub array antennas. It is that communication method between USRP RIO and Host PC use PCI express x4 to minimize delay of data to transmit and receive. The implemented system show high error vector magnitude performance above 32 dBc and to transmit and receive HD video in experiment environment anywhere. The proposed hybrid beam forming system could be used not only in the future 5G mobile communication systems under 6 GHz frequency band but also in the systems over 6 GHz frequency band like ones in mmWave frequency bands.

• Journal of electromagnetic engineering and science
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• v.16 no.4
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• pp.229-231
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• 2016

A 180-GHz signal source based on a 65-nm CMOS technology has been developed in this study. The 180-GHz signal source consists of a 90-GHz fundamental-mode Colpitts oscillator and a 180-GHz frequency doubler. A coupled-line is employed to couple two oscillator cores for generating a differential signal, which is delivered to the input of the differential-mode doubler. The fabricated signal source operates from 181.2 to 182.4 GHz with output power varying from -15.3 to -10.8 dBm. The peak output power was -10.53 dBm at 181.3 GHz with a DC power consumption of 42 mW, and the associated phase noise was -71 dBc/Hz at 1 MHz offset.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1049-1056
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• 2016

In this paper, a design method for a compact dual-band slot antenna with bent slot is studied. Bent slots are added on the rectangular slot of the proposed antenna for dual-band operation. The rectangular slot is fed by a coaxial cable by placing a rectangular feeding patch inside the slot. When the bent slots are added onto the both corner of the upper side of the rectangular slot symmetrically, a new resonant frequency is created in low frequency because of the increasement of the slot length. A prototype of the proposed dual-band slot antenna operating at 2.45 GHz WLAN band and 4.50-8.30 GHz band including 5GHz WLAN band is fabricated on an FR4 substrate with a dimension of 30 mm by 30 mm. Experiment results show that the antenna has a desired impedance characteristic with a frequency band of 2.40-2.49 GHz and 4.33-9.85 GHz for an input reflection coefficient < -10 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.7-13
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• 2011

A mixed-mode QPSK demodulator for 60-GHz wireless personal area network application is demonstrated. In this work, mixed-mode QPKS demodulation scheme achieving low power consumption and small area is employed. The prototype chip realized by 60-nm CMOS Logic process can demodulate up to 4.8-Gb/s QPSK signals at 4.8-GHz carrier frequency. At this carrier frequency, the demodulator core consumes 54 mW from 1.2-V power supply while the chip area is $150{\times}150{\mu}m^2$. Using the fabricated chip, transmission and demodulation of 1.7-GSymbol/s QPSK signal in 60-GHz link is demonstrated.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.