• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.1
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• pp.19-24
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• 2003

Design and test results of a VRAG(Vacuum Rotary Arc Gap) switch were presented. To control the damage of electrodes caused by the vacuum arc, Lorentz's force by the radial magnetic field between spiral electrodes was used to rotate the vacuum uc. VRAG switch electrodes were made of the material of CuCr and OFHC. Gap distance between two spiral type electrodes for the rotation of the arc discharge is 8, 10, 12mm. In the cathode, one trigger electrode was inserted into each spiral wing. Normal operation of the VRAG switch was confirmed with 10.6[$mutextrm{s}$]of trigger delay and 2~3[$mutextrm{s}$] of the jitter time. The speed of the vacuum arc was measured to be 0.6 ~ 1[km/s] by a motion analyzer.

• Journal of Korea Multimedia Society
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• v.6 no.2
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• pp.301-308
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• 2003

In this paper, we propose a multicast ATM switch that reduces traffic load by using the method of storing unicast cells and multicast cells separately according to the type of the cells. The switch is based on a shared memory type to reduce HOL blocking and deadlock. In the proposed switch, we use a control scheme that schedules stored cells to output ports to reduce the loss of traffic cells and to output effectively. We analyzed the Performance of the proposed switch through the computer simulation and the results have shown the effectiveness of the switch.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.108-113
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• 2021

In this paper, a totem pole PFC was structured in two methods with FET and diode for low-speed switch while GaN FET was used for high-speed switch. Internal power loss, power conversion efficiency and steady-state characteristics of the two methods were compared in the totem pole bridgeless PFC circuit which is widely applied in large-capacity and high-efficiency switching rectifier of 500W or more. In order to compare and confirm the steady-state characteristics under equal conditions, a 2kW class totem pole bridgeless PFC was constructed and the experimental results were analyzed. From the experimental results, it was confirmed that the low-speed switch operation has a large difference in efficiency due to the internal conduction loss of the low-speed switch at a low input voltage. Especially, input power factor and load characteristic showed no difference regardless of the low-speed switch operation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.5
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• pp.950-959
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• 2009

In this paper, a dc link voltage variable inverter system is proposed, which consists of a two-switch buck-boost converter and a four-switch inverter. In addition, as the current and torque ripples are generated by a voltage difference between back EMF and dc link voltage, these ripples could be reduced according to the controlled dc-link voltage according to the motor speed. The validity of the proposed inverter is verified by informative simulation and experimental results.

• Journal of Communications and Networks
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• v.18 no.3
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• pp.523-530
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• 2016

We use both theoretical analysis and simulations to study the impact of crosspoint-queued (CQ) buffer size on CQ switch throughput and delay performance under different traffic models, input loads, and scheduling algorithms. In this paper, we present the following. 1) We prove the stability of CQ switch using any work-conserving scheduling algorithm. 2) We present an exact closed-form formula for the CQ switch throughput and a non-closed-form but convergent formula for its delay using static non-work-conserving random scheduling algorithms with any given buffer size under independent Bernoulli traffic. 3) We show that the above results can serve as a conservative guide on deciding the required buffer size in pure CQ switches using work-conserving algorithms such as the random scheduling, under independent Bernoulli traffic. 4) Furthermore, our simulation results under real-trace traffic show that simple round-robin and random work-conserving algorithms can achieve quite good throughput and delay performance with a feasible crosspoint buffer size. Our work reveals the impact of buffer size on the CQ switch performance and provides a theoretical guide on designing the buffer size in pure CQ switch, which is an important step toward building ultra-high-speed switch fabrics.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.7
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• pp.60-66
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• 2005

This paper presents the single-stage TSFC(Two-Switch Forward Converter). Recently, due to growing concern about the harmonic pollution of power distribution systems and the adoption of standards such as ICE 61000-3-2 and IEEE 519, There is a need to reduce the harmonic contests of AC line currents of power supplies. This research proposed the single-stage two switch forward circuit for low voltage and high current output. The principle of operation, feature and design considerations is illustrated and verified through the experiment with a 200[W](5[V], 40[A]) 100[kHz] MOSFET based experimental circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.1003-1009
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• 2005

In this paper, small-size high-power single pole double throw(SPDT) switch with defected pound structure(DGS) is presented for wireless broadband internet application. To reduce the circuit size using slow-wave characteristic, the DGS is applied to ${\lambda}/4$ transmission line of the switch and the measured results are compared with them of conventional switch. To secure high degree of isolation, the switch with the DGS is composed of shunt-connected PIN diodes and shows insertion loss of 0.8 dB and isolation more than 50 dB at 2.3 GHz. The size of the switch is reduced about $50\%$ only with the DGS patterns while it has very similar performance to the conventional shunt-type switch.

• Journal of Power Electronics
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• v.16 no.2
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.8
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• pp.52-58
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• 2008

Ths paper describes the Dual-band switch which was proposed new structure that could improved the specification of broadband and designed by the optimized structure through simulation. The Dual-band switch with 2.4[GHz]/5.8[GHz] that can apply to 802.11a/b/g system that is commercialized present was studied to get a new structure with higher power, high isolation. The transmitter of switch was designed to operate a parallel switching element with stack structure of two FET. The receiver designed to have asymmetry structure that insert series FET in addition to basic serial/parallel FET. SPDT(Single Pole Double Throw) Tx/Rx FET switch is a device that can do switching from a port of input to two port of output. The fabricated SPDT switch has the characteristic of insertion loss of a below -3[dB] form DC to 6[GHz] and the isolation of a below -30D[dB](Rx mode).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.364-371
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• 2007

In this paper, the design and implementation of high-power PIN diode switch modules and high-speed switch driver circuits are presented for Wibro base stations. To prevent isolation degradation due to parasitic inductances of conventional packaged PIN diodes and to improve power handling capabilities of the switch modules, bare diode chips are used and carefully placed in a PCB layout, which makes bonding wire inductances to be absorbed in the impedance of a transmission line. The switch module is designed and implemented to have a maximum performance while using a minimum number of the diodes. It shows an insertion loss of ${\sim}0.84\;dB$ and isolation of 80 dB or more at 2.35 GHz. The switch driver circuit is also fabricated and measured to have a switching speed of ${\sim}200\;nsec$. The power handling capability test demonstrates that the module operates normally even under a digitally modulated 70 W RF signal stress.