• Journal of Information Processing Systems
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• v.17 no.1
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• pp.191-202
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• 2021

In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program's computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

• Journal of Korea Multimedia Society
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• v.3 no.3
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• pp.263-271
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• 2000

In this paper, an acoustic echo canceller(AEC) is implemented by ADSP-2181. This AEC uses a noise robust adaptive algorithm and a postprocessing method which attenuates residual echo using cross-correlation between estimated error signal and microphone input signal. We propose new postprocessing method that uses two thresholds to prevent signal distortion after postprocessing and to improve the performance of AEC without extra computational burden. Through experiments using a 16 bit fixed-point DSP board (ADSP-2181 EZ-KIT Lite board), it is shown that the noise robust adaptive algorithm performs well in the double-talk situations and the convergence speed is comparable to NLMS. Using the postprocessor, ERLE is improved about 20 dB. As a result, the AEC with a postprocessor shows better performance than conventional ones.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.5
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• pp.997-1006
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• 2019

To overcome the difficulties and inefficiencies of the existing power analysis attack, we try to extract the secret key embedded in a cryptographic device using attack model based on MLP(Multi-Layer Perceptron) method. The target of our proposed power analysis attack is the AES-128 encryption module implemented on an 8-bit processor XMEGA128. We use the divide-and-conquer method in bytes to recover the whole 16 bytes secret key. As a result, the MLP-based power analysis attack can extract the secret key with the accuracy of 89.51%. Additionally, this MLP model has the 94.51% accuracy when the pre-processing method on power traces is applied. Compared to the machine leaning-based model SVM(Support Vector Machine), we show that the MLP can be a outstanding method in power analysis attacks due to excellent ability for feature extraction.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2
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• pp.50-61
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• 1995

A time scale modification method yielding rate-modified speech while conserving the characteristic of speech was implemented in real-time using a goneral purpose digital signal processor. Time scale modification changed pronunciation speed only, producing a time difference between the input signal and the modified signal, making it impossible to implement it in real-time. In this thesis, a system was implemented to remove the time difference between the input and modified signals. Speech signals slowed down or speeded up by a physical time scale modification method, such as adjusting the motor speed of the cassett tape recorder, was used as the input signal. Physical modification that controled only the inter speed of the cassette tape player distorted the pitch period of the original speech. In this study, a real-time system was implemented so that the pitch-distorted speech was reconstructed back to the original by fractional sampling pitch shifting using an FIR filter, and this signal was time scale modified to match the cassette tape recorder motor speed using SOLA time-scale medification. In experiments using speech signals medifiedby the proposed method, results obtained using a 16-bit resolution ADSP2101 processor and using computer simulations employing floating point operations showed about the same average frame signal-to-noise ratio of about 20 dB.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.5
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• pp.17-30
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• 2001

In this paper, we implemented a scalar multiplier needed at an elliptic curve cryptosystem over standard basis in $GF(2^{163})$. The scalar multiplier consists of a radix-16 finite field serial multiplier and a finite field inverter with some control logics. The main contribution is to develop a new fast finite field inverter, which made it possible to avoid time consuming iterations of finite field multiplication. We used an algorithmic transformation technique to obtain a data-independent computational structure of the Extended Euclid GCD algorithm. The finite field multiplier and inverter shown in this paper have regular structure so that they can be easily extended to larger word size. Moreover they can achieve 100% throughput using the pipelining. Our new scalar multiplier is synthesized using Hyundai Electronics 0.6$\mu\textrm{m}$ CMOS library, and maximum operating frequency is estimated about 140MHz. The resulting data processing performance is 64Kbps, that is it takes 2.53ms to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption & decryption and key exchange in real time embedded-processor environments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Publications of The Korean Astronomical Society
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• v.21 no.2
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• pp.67-74
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• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).