• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.1-8
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• 2007

A wideband continuous-time sigma delta modulator for wireless application is implemented in 130nm CMOS. The SNR for small input signal is improved using a proposed adaptive quantizer which can effectively scale the quantization level. The modulator comprises a second-order loop filter for low power consumption, 4-bit quantizer and DAC for low jitter sensitivity and high linearity. Designed circuit achieves peak SNR of 51.36B with 10MHz signal Bandwidth and 320MHz sampling frequency dissipating 30mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.43-51
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• 2013

This paper presents a design and implementation of a low power switched-capacitor 3rd-order delta-sigma modulator for a digital hearing-aid application. The power consumption is reduced by minimizing the output swing of integrators through optimizing the coefficients of modulator architecture and using class-AB output operational amplifiers. The modulator was implemented in a 130nm CMOS technology, and measured to have 79dB of SNR(Signal-to-Noise Ratio) in the signal bandwidth between 100Hz and 10kHz with an oversampling ratio of 160. The power consumption was $60{\mu}W$ from 1.2V power supply and the modulator core occupied $0.53mm{\times}0.53mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.292-299
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• 2015

An envelope elimination and restoration transmitter that uses a tri-level envelope encoding scheme is presented for improving the efficiency and linearity of the system. The proposed structure amplifies the same magnitude signal regardless of the input peak-to-average power ratio and reduces the quantization noise by spreading out the noise to the out-of-band frequency, resulting in the enhancement of power efficiency. An improved linearity is also obtained by providing a new timing mismatch calibration technique between the envelope and phase signal. Implementation in a 130 nm CMOS process, transmitter measurements on a 20-MHz long-term evolution input signal show an error vector magnitude of 3.7 % and an adjacent channel leakage ratio of 37.5 dBc at 2.13 GHz carrier frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.8
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• pp.632-639
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• 2018

This paper presents a single antenna radar sensor with a Ku-band radar transceiver IC realized by 130 nm CMOS processes. In this radar receiver, sensitivity time control using a DC offset cancellation feedback loop is employed to achieve a constant SNR, irrespective of distance. In addition, the receiver RF block has gain control to adjust high dynamic range. The RF output power is 9 dBm and the full chain gain of the Rx is 82 dB. To reduce the direct-coupled Tx signal to the Rx in a single antenna radar, a stub-tuned hybrid coupler is adopted instead of a bulky circulator. The maximum measured distance between the horn antenna and a metal plate target is 6 m.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.249-254
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• 2011

This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of IKEEE
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• v.21 no.3
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• pp.185-194
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• 2017

In this paper, a modular platform for wearable devices is proposed which can be easily assembled by exchanging functions according to various field and environment conditions. The proposed modular platform consists of a 32-bit RISC CPU, a 32-bit symmetric multi-core processor, and a 16-bit DSP. It also includes a plug & play features which can quickly respond to various environments. The sensing and communication modules are connected in the form of a chain. This work is implemented in a standard 130 nm CMOS technology and the proposed modular wearable platforms are verified with temperature and humidity sensors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.