• Title/Summary/Keyword: 12 인치 Si wafer

Search Result 3, Processing Time 0.017 seconds

Development of an Atmospheric Pressure Plasma Source for Resist Removal on 12 Inch Si Wafers

  • Yu, Seung-Yeol;Seok, Dong-Chan;Park, Jun-Seok;Yu, Seung-Min;No, Tae-Hyeop
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2012.02a
    • /
    • pp.488-488
    • /
    • 2012
  • 상압에서 12인치 실리콘 웨이퍼 표면처리가 가능한 장치를 개발하였다. 배치타입 공정으로 플라즈마 발생 전극은 직경 340 mm의 대면적 원형 형태을 가지고 있다. 시스템은 탈부착이 가능한 플라즈마 모듈부와 공정챔버로 나누어지며 균일도를 높이기 위해 웨이퍼스테이지는 가열, 회전 및 축간 조절이 가능하게 설계하였다. 플라즈마발생은 DBD 전극방식을 채용하고 있으며 공정가스흐름 및 전극배열 등을 연구하였다. 또한, 기판 온도, 가스 조합 등의 공정파리미터를 변화시켜가며 높은 애슁 속도 및 균일도를 얻기 위한 실험이 진행되었다. 주파수 15 kHz, 인가 파워 7 kW, 시편 가열 온도 95도, 60 rpm, 80 spm에서 분당 200 nm의 PR제거율을 확인하였다.

  • PDF

A Study on the Optimal Machining of 12 inch Wafer Polishing by Taguchi Method (다구찌 방법에 의한 12인치 웨이퍼 폴리싱의 가공특성에 관한 연구)

  • Choi, Woong-Kirl;Choi, Seung-Gun;Shin, Hyun-Jung;Lee, Eun-Sang
    • Journal of the Korean Society of Manufacturing Process Engineers
    • /
    • v.11 no.6
    • /
    • pp.48-54
    • /
    • 2012
  • In recent years, developments in the semiconductor and electronic industries have brought a rapid increase in the use of large size silicon. However, for many companies, it is hard to produce 400mm or 450mm wafers, because of excesive funds for exchange the equipments. Therefore, it is necessary to investigate 300mm wafer to obtain a better efficiency and a good property rate. Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This research investigated the surface characteristics that apply variable machining conditions and Taguchi Method was used to obtain more flexible and optimal condition. In this study, the machining conditions have head speed, oscillation speed and polishing time. By using optimum condition, it achieves a ultra precision mirror like surface.

Fabrications and Analysis of Schottky Diode of Silicon Carbide Substrate with novel Junction Electric Field Limited Ring (새로운 전계 제한테 구조를 갖는 탄화규소 기판의 쇼트키 다이오드의 제작과 특성 분석)

  • Cheong Hui-Jong;Han Dae-Hyun;Lee Yong-Jae
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.10 no.7
    • /
    • pp.1281-1286
    • /
    • 2006
  • We have used the silicon-carbide(4H-SiC) instead of conventional silicon materials to develope of the planar junction barrier schottky rectifier for ultra high breakdown voltage(1,200 V grade). The substrate size is 2 inch wafer, Its concentration is $3*10^{18}/cm^{3}$ of $n^{+}-$type, thickness of epitaxial layer $12{\mu}m$ conentration is $5*10^{15}cm^{-3}$ of n-type. The fabticated devices are junction barrier schottky rectifier, The guard ring for improvement of breakdown voltage is designed by the box-like impurity of boron, the width and space of guard ring was designed by variation. The contact metals to rectify were used by the $Ni(3,000\:{\AA})/Au(2,000\:{\AA})$. As a results, the on-state voltage is 1.26 V, on-state resistance is $45m{\Omega}/cm^{3}$, maximum value of improved reverse breakdown voltage is 1180V, reverse leakage current density is $2.26*10^{-5}A/CM^{3}$. We had improved the measureme nt results of the electrical parameters.