• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6A
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• pp.648-656
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• 2007

This paper is about band pass filter, using Ceramics in the condition of center frequency 370Hz at milli-wave. The band pass filter is applied to Broadband Convergence Network, representing WLL(Wireless Local Loop) and LMDS(Local Multi-point Distribution Service). Sticking ceramic between strip line on a dielectric material substrate with which conductor's covers upper and basal surface, One will house the exterior by using structural resonance. In this Non Radiative Microstrip Line Filter structure, based upon simulations, generalized the two formulas finding resonant frequency of 1step ceramic resonator and bandwidth of 4step ceramic resonator. Also, As a result of experiment, using Network Analyzer, about created a experiment of structure based on the simulation result of 4-step ceramic resonator, It showed good characteristic of targeted bandwidth, comparing simulated result of 36.58GHz$\sim$37.650GHz with experimented result of 36.6GHz$\sim$37.65GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1292-1296
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• 2002

In this paper, a 3-coupled microstrip line tunable bandpass filter has been designed on the basis of a tonductoriFerroelectricfDielectric (CFD) structure. This tunable filter basically exploits the fact that the increase in the bias voltage leads to the reduction of the effective dielectric constant (eon). This reduced $\varepsilon$eff shifts the center frequency (fc) to the higher value. The characteristics of designed filter are as follows; Return loss (RL) is larger than 10 dB; Insertion loss (IL) is les.i than 3.5 dB: 3-dB bandwidth (BW) is less than 1.18 GHz fc can be tuned from 25.4 GHz to 28.8 GHz over the variation of $\varepsilon$eff, from 10 to 13. Therefore, the tunability comes up to 3.4 GHz. The dimension of the filter designed is 7.0 mm ${\times}$ 5.0 nm ${\times}$ 0.5 mm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.43-46
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• 2018

This paper has designed a wideband bandpass filter (WBSF : Wide Band Stop Filter) using a stepped impedance resonator (SIR : Stepped Impedance Resonator) with improved performance and improved hairpin coupling structure. The SIR WBSF is small in size and has the advantage of having excellent bandstop characteristics. The designed BSF has a structure in which a quadrangular shaped hairpin of a / 4 length is arranged symmetrically on the upper and lower sides of the input and output transmission lines. The input and output terminals were terminated at 50 ohms for system applications. The center frequency of the SIR WBSF is 6.3 GHz, which is the second harmonic of 3.15 GHz. The designed filter has a 3dB bandwidth of 2.9 GHz and a transmission coefficient ($S_{21}$) of 33.2 dB. The reflection coefficient ($S_{11}$) at the center frequency is 0.106 dB. The application field is used for fixed microwave relay stations, fixed satellite and earth stations, and fixed satellite communications. The overall size is $20mm{\times}10mm$.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.3
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• pp.19-24
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• 1999

The multilayer chip band pass filter for mobile communication is fabricated and designed. The size, insertion loss, center frequency and band width of multilayer chip filter are 4.5$\times$4.4$\times$1.8[mm], 3.0[dB] and 700[MHz]$\pm$15[MHz] respectively. The chip filter using $BiNbO_4$with CuO 0.06wt% +$V_2O_5$.lwt% was fabricated by screen printing with Ag electrode after tape casting. Insertion loss and center frequency of the fabricated chip filter are 2.58[dB] and 692.5$\pm$15[MHz] respectively. The center frequency was lower 7.5[MHz] than design result, but other characteristics of chip filter were similar to the ruts ultras of design result.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.8
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• pp.1464-1469
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• 2008

A CMOS Gm-C filter with variable cutoff frequency applicable for using in the direct conversion receiver is designed. The designed filter comprises the CMOS differential transconductors, and the gm of the transconductor is controlled by the bias voltage. This configuration can compensate variant of the cutoff frequency which could be generated by external noises, and also be used in multiband receiver. As a results of HSPICE simulation, the control range of the cutoff frequency is $1.5MHz{\sim}3.5MHz$ and the gain control range is $-2.8dB{\sim}2.6dB$. The layout of the designed 5th-order Elliptic low-pass filter is performed to fabricate a chip using $2.5V-0.25{\mu}m$ CMOS processing parameter.

• Journal of electromagnetic engineering and science
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• v.10 no.1
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• pp.1-5
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• 2010

A spurious suppressed bandpass filter is proposed and discussed using the stepped impedance resonator(SIR) on a substrate-integrated waveguide(SIW) structure with a double-layer substrate. The second resonance of the fundamental $TE_{10}$ mode can be controlled by adjusting the electrical length and impedance ratio of each SIR. The spurious suppressed SIW bandpass filter shows the measurement results of the insertion loss of 3.98 dB and return loss of less than 11.58 dB at the center frequency of 12 GHz. Also, the second spurious frequency is improved to about $1.5f_0$ compared with $1.33f_0$.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.893-896
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• 2005

This paper describes Low Noise Amplifier(LNA) and Single Balanced Mixer(SBM) with monolithic image rejection notch filter using 0.5um MESFET process. LNA, Notch filter, and SBM were integrated on a chip. This chip does not need off chip SAW filter, thereby reducing the overall cost and system volume. The LNA with Notch filter provides a gain of 15dB, noise figure of 1.2dB, and image rejection ratio of -74dB. The SBM has a conversion gain of 6dB.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1497-1500
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• 2006

Inkjet printing technology can reduce the LCD color filter manufacturing cost more than 50 %. Uniform color filter patterning can be achieved only with proper ink and barrier materials. We developed new ink and black matrix materials for inkjet color filter. The ink materials have low volatility while they have very high solid content. The black matrix materials have very precisely controlled surface energy so that the inks can fill the pixels evenly and completely. We controlled the ink drop volume and ink material to minimize the thickness difference between the black matrix and the color pixel. Micron-order jetting position accuracy was achieved. We successfully printed 14.1" color filters using our ink and black matrix materials.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.242-244
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• 1987

Using the energy trapping theory and the acoustic coupling theory. the Bandpass filter(center frequency = 10.7 MHz) of the fundamental thickness mode was made from the composition of $Pb_{0.96}Sr_{0.04}(Zr_{0.53}Ti_{0.47})O_3$+ 1wt% $Fe_2O_3$. Also, in the double mode monolithic filter, It was observed that as decreasing the size of the electrodes, or shortening the gap between two electrodes, the percent frequency separation was increased. Based on these. a 10.7 MHz uniwafer filter was made having the characteristics that bandwidth was 700 KHz and the percent frequency separation was 6 [dB] and selectivity was 29 [dB], end spurious response was 24 [dB] and insertion loss was 7 [dB].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.