• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.40-45
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• 2008

We developed small molecular organic nonvolatile $4F^2$ memory cells using metal layer evaporation followed by $O_2$ plasma oxidation. Our memory cells sandwich an upper ${\alpha}$-NPD layer, Al nanocrystals surrounded by $Al_2O_3$, and a bottom ${\alpha}$-NPD layer between top and bottom electrodes. Their nonvolatile memory characteristics are excellent: the $V_{th},\;V_p$ (program), $V_e$ (erase), memory margin ($I_{on}/I_{off}$), data retention time, and erase and program endurance were 2.6 V, 5.3 V, 8.5 V, ${\approx}1.5{\times}10^2,\;1{\times}10^5s$, and $1{\times}10^3$ cycles, respectively. They also demonstrated symmetrical current versus voltage characteristics and a reversible erase and program process, indicating potential for terabit-level nonvolatile memory.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.

• 한국결정성장학회지
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• 제12권6호
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• pp.304-310
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• 2002

실리콘 기판 위의 초기 산화막을 NO 열처리 및 재산화 공정방법으로 성장한 재산화된 질화산화막을 게이트 유전막으로 사용한 새로운 전하트랠형 기억소자로의 응용가능성과 계면트랩특성을 조사하였다. 0.35$\mu$m CMOS 공정기술을 사용하여 게이트 유전막은 초기산화막을 $800^{\circ}C$에서 습식 산화하였다 전하트랩영역인 질화막 층을 형성하기 위해 $800^{\circ}C$에서 30분간 NO 열처리를 한 후 터널 산화막을 만들기 위해 $850^{\circ}C$에서 습식 산화방법으로 재산화하였다. 프로그램은 11 V, 500$\mu$s으로 소거는 -l3 V, 1 ms의 조건에서 프로그래밍이 가능하였으며, 최대 기억창은 2.28 V이었다. 또한 11 V, 1 ms와 -l3 V, 1 ms로 프로그램과 소거시 각각 20년 이상과 28시간의 기억유지특성을 보였으며 $3 \times 10^3$회 정도의 전기적 내구성을 나타내었다. 단일접합 전하펌핑 방법으로 소자의 계면트랩 밀도와 기억트랩 밀도의 공간적 분포를 구하였다. 초기상태에서 채널 중심 부근의 계면트랩 및 기억트랩 밀도는 각각 $4.5 \times 10^{10}/{cm}^2$ 와 $3.7\times 10^{1R}/{cm}^3$ 이었다. $1 \times 10^3$프로그램/소거 반복 후, 계면트랩은 $2.3\times 10^{12}/{cm}^2$으로 증가하였으며, 기억트랩에 기억된 전하량은 감소하였다.