• Journal of Digital Convergence
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• v.10 no.11
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• pp.371-376
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• 2012

In this paper, we propose a new data coding method and its circuits for minimizing data transition in text image. The proposed circuits can solve the synchronization problem between input data and output data in the modified LVDS algorithm. And the proposed algorithm is allowed to transmit two data signals through additional serial data coding method in order to minimize the data transition in text image and can reduce the operating frequency to a half. Thus, we can solve EMI(Electro-Magnetic Interface) problem and reduce the power consumption. The simulation results show that the proposed algorithm and circuits can provide an enhanced data transition minimization in text image and solve the synchronization problem between input data and output data.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.12
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• pp.391-398
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• 2015

This paper devises a performance improvement and evaluation process of circuit minimization algorithms for mentorship education of distinguished informatics gifted secondary students. In the process, students learn that there are several alternative equivalent circuits for a target function and recognize the necessity for formalized circuit minimization methods. Firstly, they come at the concept of circuit minimization principle from Karnaugh Map which is a manual methodology. Secondly, they explore Quine-McCluskey algorithm which is a computational methodology. Quine-McCluskey algorithm's time complexity is high because it uses set operations. To improve the performance of Quine-McCluskey algorithm, we encourage them to adopt a bit-wise data structure instead of integer array for sets. They will eventually see that the performance achievement is about 36%. The ultimate goal of the process is to enlarge gifted students' interest and integrated knowledge about computer science encompassing electronic switches, logic gates, logic circuits, programming languages, data structures and algorithms.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.550-553
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• 1998

본 논문에서는 노드들간의 입출력 관계가 트리형태로 주어진 경우에 이 관계를 수식으로 해석하여 최소화시키고 이를 회로로 구현하는 새로운 알고리즘을 제안한다. nakagima 등에 의해 제안된 알고리듬은 트리의 특성을 갖는 노드들의 관계를 2치논리에 근거하여 회로로 구현하였으나, 이러한 기법은 일반적인 형태로 주어진 트리구조에 대한 해석이 충분치 못하므로, 일반화된 회로의 구성에 많은 제약을 가지고 있다. 이러한 문제점에 대하여 본 논문에서는 트리구조를 갖는 노즈들의 전체적인 입출력관계를 수식으로 정리하여 최소화된 회로설계 알고리즘을 제안하고 예를 들어 이를 검증한다.

• Proceedings of the KIEE Conference
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• 1985.07a
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• pp.249-253
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• 1985

본 논문은 후술할 다출력 스위칭 회로의 최소성 기준(Criteria of Minimality)에 의한 최소의 다출력 스위칭 회로를 설계하는 데 목적을 두고 있다. 이에는 단일 출력 스위칭 함수에 적용된 바 있는 Direction of Adjacency Table 방법이 다소 변경되어 다출력 스위칭 회로에 적용되었다. 이르 위하여 기존의 Direction of Adjacency Table을 다출력 함수의 최소화에 적합하도록 변경한 Extended Direction of Adjacency Table이 구성된다.

• Proceedings of the Acoustical Society of Korea Conference
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• 1993.06a
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• pp.242-246
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• 1993

예측신경회로망 모델은 다층 퍼셉트론을 연속되는 음성특징 벡터간의 비선형예측기로 사용하는 동적인 음성인식 모델이다. 이 모델은 음성의 동적인 특성을 인식에 이용하고 연속음성인식으로의 확장이 용이한 우수한 인식 모델이다. 그러나, 예측신경회로망 모델은 음운학적으로 유사한 음성구간에서의 변별력이 낮다는 문제점이 있다. 그것은 기존의 학습 알고리즘이 다른 어휘와의 거리는 고려하지 않고 대상어휘의 예측오차만 최소화시키기 때문이다. 따라서, 본 논문에서는 직접 인식오차를 최소화시키는 GPD알고리즘에 의해 유사어휘간의 거리를 고려하는 변별력있는 학습 알고리즘을 제안한다.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.95-102
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• 2015

This paper proposes a simple algorithm for circuit minimization. There are currently two effective heuristics for circuit minimization, namely manual Karnaugh maps and computable Quine-McCluskey algorithm. The latter, however, has a major defect: the runtime and memory required grow $3^n/n$ times for every increase in the number of variables n. The proposed algorithm, however, extracts the prime implicants (PI) that cover minterms of a given Boolean function by deriving an implicants table based on frequency. From a set of the extracted prime implicants, the algorithm then eliminates redundant PIs again based on frequency. The proposed algorithm is therefore capable of minimizing circuits polynomial time when faced with an increase in n. When applied to various 3-variable and 4-variable cases, it has proved to swiftly and accurately obtain the optimal solutions.

• Journal of the Korea Society of Computer and Information
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• v.19 no.3
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• pp.109-117
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• 2014

This paper revises the Quine-McCluskey Algorithm to circuit minimization problems. Quine-McCluskey method repeatedly finds the prime implicant and employs additional procedures such as trial-and-error, branch-and-bound, and Petrick's method as a means of circuit minimization. The proposed algorithm, on the contrary, produces an implicant chart beforehand to simplify the search for the prime implicant. In addition, it determines a set cover to streamline the search for $1^{st}$ and $2^{nd}$ essential prime implicants. When applied to 3-variable and 4-variable experimental data, the proposed algorithm has indeed proved to obtain the optimal solutions much more simply and accurately than the Quine-McCluskey method.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.504-511
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• 2003

The property of circuit symmetry has long been applied to the Problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power minimization, utilizing circuit symmetries. First, we analyze and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose effective transformation algorithms to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.12-21
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• 1999

All kinds of electronic machinery including portable communication system are being smaller size and are used at high frequency. It generates a lot of unwanted noise signals called electromagnetic interface (EMI). This paper presents an analysis result of EMI generation in VLSI and propose new circuits to minimize of EMI using I/O driver with parallel buffer architecture and distributed decoupling capacitor in a chip. The proposed circuits are evaluated with i8052 MCU which is shown reducing of delta current 1/3 times and improvement of EMI more 10dBuV compared with conventional processors.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2329-2331
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• 2004

본 논문에서는 이동 로봇의 경로 추종 제어를 위해 웨이블릿 신경 회로망에 기반한 예측 제어기의 설계 방법을 제안하고자 한다. 제안한 방법에 의해 설계된 제어기는 이동 로봇의 동특성을 예측하기 위한 웨이블릿 신경회로망 기반 예측기와 예측 제어기로 구성된다. 제안한 방법에서 모델링 및 제어기로 적용되는 신경 회로망의 장점과 우수한 해석 능력을 가진 웨이블릿 변환의 장점을 결합한 웨이블릿 신경 회로망을 이용하여 이동 로븟의 동특성을 모델링하여 예측 제어기에서의 비용 함수 최소화에 적용한다. 경로 추종 제어의 목적인 이동 로봇의 실제 출력과 예측기의 출력 오차를 최소화하기 위해 웨이블릿 신경 회로망의 파라미터 동정 및 예측 제어기는 경사 하강법을 이용하여 학습한다. 마지막으로 컴퓨터 모의 실험을 통하여 제안한 예측 제어 시스템의 적용가능성 및 효율성을 검증하고자 한다.