• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2426-2438
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• 1994

In this paper we present for the first time the electric circuit model for direct frequrncy modulation(FM) response of the conventional distributed-feedback(DFB) semiconductor laser diodes. Especially, in this paper, the proposed model includes not only the carrier density modulation effect, but also the temperature modulation effect determining the DFM characteristics of DFB characteristics of DFB semiconductor lasers. The DFM response due to injection current modulation was obtained as a function of modulation frequency from DC to a few GHz. The circuit model representing the temperature modulation effect is obtained from the structure of DFB LD chip and the simulation results are compared with the published experimental results. The circuit model representing the temperature modulation effect is obtained from the structure of DFB LD chip and the simulation results are compared with the published experimental results. The circuit model representing carrier density modulation effect is obtained from the rate equations of DFB lasers and the simulation results are compared with the results that were obtained by the conventional numerical analysis approach. The results showed good agreements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.49-56
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• 2005

In this paper, we propose a memory BIST Circuit Creation System which creates BIST circuit based on user defined fault model and generates the optimized march test algorithm. Traditional tools have some limit that regenerates BIST circuit after changing the memory type or test algorithm. However, this proposed creation system can automatically generate memory BIST circuit which is suitable in the various memory type and apply algorithm which is required by user. And it gets more efficient through optimizing algorithms for fault models which is selected randomly according to proposed nile. In addition, it support various address width and data and consider interface of IEEE 1149.1 circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.634-636
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• 2021

In this study, we studied the macro-modeling of an feedback field-effect transistor (FBFET) using SPICE simulation. The previously presented macro-model of the FBFET is consisting of two circuits. one is charge integration circuit, and the other is current generation circuit. The previous current generation circuit has problem that can't predict performance accurately of the circuits, due to implementing only I_DS-V_GS characteristics. To solve this problem, we presents a model that can implement not only I_DS-V_GS characteristics but alos I_DS-V_DS characteristics by adding the diode in the current generation circuit.

• Bulletin of the Korean Space Science Society
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• 1998.10a
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• pp.62-62
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• 1998

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2977-2979
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• 1999

본 논문에서는 MEBP(Modified Error Back-Propagation) 학습 규칙을 간단한 비선형 회로를 이용하여 구현하였다. 인공 신경 회로망(ANNs : Artificial Neural Networks)은 많은 수의 뉴런을 필요하기 때문에 표준 CMOS 기술을 이용하는 간단한 비선형 시냅스(synapse) 회로는 인공 신경 회로망 구현에 적합하다. 학습회로는 비선형 시냅스 회로. 시그모이드(sigmoid) 회로. 그리고 선형 곱셈기로 구성되어 있다. 학습 회로의 출력은 각 입력 패턴에 따라 유일한 값으로 결정되어진다. 제안한 학술회로를 $2{\times}2{\times}1$과 $2{\times}3{\times}1$ 다층 feedforward 신경 회로망 모델에 적용하였다. MEBP 하드웨어 구현은 HSPICE 회로 시뮬레이터를 이용하여 검증하였다. 제안한 학술 회로는 on-chip 학습회로를 포함한 대규모 신경회로망 구현에 매우 적합하리라 예상된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.83-91
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• 2000

This paper presents a new technique to reduce a large interconnect circuit with tens of thousands of elements into the one that is small enough to be analyzed by circuit simulators such as SPICE. This technique takes a fundamentally different approach form the conventional methods based on the interconnect circuit structure analysis and several rules based on the Elmore time constant. The time moments are computed form the circuit consisting of the interconnect circuit and the CMOS gate driver model computed by the AWE technique. Then, the equivalent RC circuit is synthesized from those moments. The characteristics of the driving CMOS gate can be reflected with the high degree of accuracy and the size of the compressed circuit is determined by the number of output nodes regardless of the size of the original interconnect circuits. This technique has been implemented in C language, applied to several interconnect circuits driven by a 0.5${\mu}m$ CMOS gate and the equivalent RC circuits with more than 99% reduction ratio and accuracy with 1 ~ 10% error in therms of propagation delays were obtained.

• Proceedings of the Korea Society for Simulation Conference
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• 2000.11a
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• pp.131-134
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• 2000

본 논문에서는 디지털 IC회로의 입출력과 입출력 버퍼에 대한 입출력 버퍼정보 형식 모델링을 묘사하였고 입출력 버퍼의 전기적 특성을 표현하는 방법 등을 나타냈다. 또한 본 논문에서 도출한 입출력 버퍼 모델링은 CMOS와 TTL IC를 모델링 하는데 사용할 수 있는데 CMOS와 TTL IC 그리고 ROM과 RAM 메모리에 대한 입출력 버퍼 모델을 128개 정도 만들었다. 이러한 입출력 버퍼 모델은 정확한 행동(behavioral) 모델을 구성하기 위해 그리고 고속 회로의 PCB 디자인 시뮬레이션에 사용될 것이다.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.6
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• pp.44-49
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• 1997

백열전구 시스템의 설계에서 스너버 회로의 설계는 백열전구의 특성을 고려하는 것이 대단히 중요하다. 특히 서지전압 유입시 백열전구의 과도특성은 설계시 보다 많은 설계사양들을 제공하게 된다. 본 논문에서는 서지전압 유입시 과도특성에 근거한 백열전구의 동작모델을 등가회로로 나타냈다. 이 모델은 제조사가 다른 백열전구에도 광범위한 적용이 가능하다. 본 논문에서 제시한 모델이 실질적으로 효용성이 있음을 나타냈으며, 스너버 회로와 리액턴스(LS) 설계시 백열전구의 서지전압 및 과도 특성에 의한 최적설계를 더욱 명확히 할 수 있다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.18-28
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• 1999

A new equivalent circuit model of package (SOP, Small Outline Package) is presented for designing radio frequency integrated circuits (RFIC). In the RF region, the paddle of a package does not work as an ideal ground. Further parasitics due to both coupling and loss have a substantial effect on MMIC. The equivalent circuit model and parameter extraction methodology for the electrical characteristics of the package are described by illustrating the SOP type packages. The accuracy of the model is evaluated by comparing the s-parameters of the commercial full-wave solver and those of HSPICE simulation with the circuit model. The proposed model shows an excellent agreement with full-wave analysis up to about 8GHz.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.131-134
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• 1997

McT는 MOS-게이트형 사이리스터로써 MOS-게이트형 턴-온 및 턴-오프 특성과 낮은 도통 전압을 나타내는 소자이다. 그러나 SOA(Safe Operation Area)가 상대적으로 작기 때문에 스너버 회로를 필요로 한다. 본 논문에서는 간단한 MCT PSPICE 모델을 사용하여 스위칭 특성과 RCD 스너버의 특성을 분석하였고 스너버 회로 설계방식을 제안하였다.