• Journal of the Korean Society for Precision Engineering
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• v.19 no.5
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• pp.149-158
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• 2002

Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.

• Tribology and Lubricants
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• v.35 no.6
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• pp.330-336
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• 2019

Conditioning is a process involving pad surface scraping by a moving metallic disk that is electrodeposited with diamond abrasives. It is an indispensable process in chemical-mechanical planarization, which regulates the pad roughness by removing the surface residues. Additionally, conditioning maintains the material removal rates and increases the pad lifetime. As the conditioning continues, the pad profile becomes unevenly to be deformed, which causes poor polishing quality. Simulation calculates the density at which the diamond abrasives on the conditioner scratch the unit area on the pad. It can predict the profile deformation through the control of conditioner dwell time. Previously, this effect of the diamond shape on conditioning has been investigated with regard to microscopic areas, such as surface roughness, rather than global pad-profile deformation. In this study, the effect of diamond shape on the pad profile is evaluated by comparing the simulated and experimental conditioning using two conditioners: a) random-shaped abrasive conditioner (RSC) and b) uniform-shaped abrasive conditioner (USC). Consequently, it is confirmed that the USC is incapable of controlling the pad profile, which is consistent with the simulation results.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.10
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• pp.156-162
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• 2002

There are many factors affecting the results of CMP (Chemical Mechanical Polishing). Among them, the temperature is related to the removal rate and WIWNU (Within Wafer Non-Uniformity). In other words, the removal rate is proportional to the temperature and the variation of temperature distribution on a pad affects the non-uniformity within a wafer. In the former case, the active chemistry improves the rate of chemical reaction and the removal rate becomes better. But, there are not many advanced studies. In the latter case, a kinematical analysis between work-piece and pad can be obtained. And such result analysed from the mechanical aspect can be directly related to the temperature distribution on a pad affecting WIWNU. Meanwhile, the temperature change affects the quantities of both slurry and pad. The change of a pH value of the slurry chemistry due to a temperature variation affects the surface state of an abrasive particle and hence the agglomeration of abrasives happens above the certain temperature. And the pH alteration also affects the zeta potential of a pad surface and therefore the electrical force between pad and abrasive changes. Such results could affect the removal rate and etc. Moreover, the temperature changes the 1st and 2nd elastic moduli of a pad which are closely related to the removal rate and the WIWNU.

• Tribology and Lubricants
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• v.31 no.3
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• pp.79-85
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• 2015

RC delay is a critical issue for achieving high performance of ULSI devices. In order to minimize the RC delay time, we uses the CMP process to introduce high-conductivity Cu and low-k materials on the damascene. The low-k materials are generally soft and fragile, resulting in structure collapse during the conventional high-pressure CMP process. One troubleshooting method is electrochemical mechanical polishing (ECMP) which has the advantages of high removal rate, and low polishing pressure, resulting in a well-polished surface because of high removal rate, low polishing pressure, and well-polished surface, due to the electrochemical acceleration of the copper dissolution. This study analyzes an electrochemical state (active, passive, transpassive state) on a potentiodynamic curve using a three-electrode cell consisting of a working electrode (WE), counter electrode (CE), and reference electrode (RE) in a potentiostat to verify an electrochemical removal mechanism. This study also tries to find optimum conditions for ECMP through experimentation. Furthermore, during the low-pressure ECMP process, we investigate the effect of current density on surface roughness and removal rate through anodic oxidation, dissolution, and reaction with a chelating agent. In addition, according to the Faraday’s law, as the current density increases, the amount of oxidized and dissolved copper increases. Finally, we confirm that the surface roughness improves with polishing time, and the current decreases in this process.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.3
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• pp.289-294
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• 2012

There are several indicators to represent characteristics of chemical mechanical planarization (CMP) such as material removal rate (MRR), surface quality and removal uniformity on a wafer surface. Especially, the removal uniformity on the wafer edge is one of the most important issues since it gives a significant impact on the yield of chip production on a wafer. Non-uniform removal rate at the wafer edge (edge effect) is mainly induced by a non-uniform pressure from nonuniform pad curvature during CMP process, resulting in edge exclusion which means the region that cannot be made to a chip. For this reason, authors tried to minimize the edge exclusion by using an edge profile control (EPC) ring. The EPC ring is equipped on the polishing head with the wafer to protect a wafer from the edge effect. Experimental results showed that the EPC ring could dramatically minimize the edge exclusion of the wafer. This study shows a possibility to improve the yield of chip production without special design changes of the CMP equipment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.79-80
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• 2007

Copper has been used as an interconnect material in the fabrication of semiconductor devices, because of its higher electrical conductivity and superior electro-migration resistance. Chemical mechanical polishing (CMP) technique is required to planarize the overburden Cu film in an interconnect process. Various problems such as dishing, erosion, and delamination are caused by the high pressure and chemical effects in the Cu CMP process. But these problems have to be solved for the fabrication of the next generation semiconductor devices. Therefore, new process which is electro-chemical mechanical planarization/polishing (ECMP) or electro-chemical mechanical planarization was introduced to solve the. technical difficulties and problems in CMP process. In the ECMP process, Cu ions are dissolved electrochemically by the applying an anodic potential energy on the Cu surface in an electrolyte. And then, Cu complex layer are mechanically removed by the mechanical effects between pad and abrasive. This paper focuses on the manufacturing of ECMP system and its process. ECMP equipment which has better performance and stability was manufactured for the planarization process.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.6
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• pp.1175-1180
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• 2022

STI has been studied a lot as a process technology for wide area planarization according to miniaturization and high integration of semiconductor devices. In this study, as methods for improving the STI profile, wet etching of pad oxide using hydrofluorine solution and dry etching of O₂+CF₄ after STI dry etching were proposed. This process technology showed improvement in profile imbalance and leakage current between patterns according to device density compared to the conventional method. In addition, as a result of measuring the HLD thickness after CMP for a device having the same STI depth and HLD deposition, the measured value was different depending on the device density. It was confirmed that this was due to the difference in the thickness of the nitride film according to the device density after CMP and the selectivity of the slurry.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2002.11a
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• pp.29-29
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• 2002

공구강 등 산업용 재료로 널리 사용되는 카바이드 계 재료는 입자 크기 및 분포에 따라 기계적 성질이 변화하므로, 이를 제어하고 조절하는 기술에 관하여 많은 연구가 진행되어 왔다. 본 연구에서는 TiCN-WC-Co 복합초경계 에서 소결 공정 및 조성변화에 따른 입자 모양을 관찰하고 이에 따른 업자 성장 거동을 고찰하였다. 일반적으로 입자 조대화 양상과 고상 입자의 모양과는 밀접한 관계가 있다. 각진 입자의 경우에 는 계면이 원자적으로 singular 하여 원자의 홉착이 어렵기 때문에 임계값 이상의 성장 구동력을 받 는 몇몇 입자만 성장하는 비정상 입자 성장이 일어날 수 있다. 반면에 계면이 rough한 퉁큰 엽자의 경우에는 원자 홉착에 필요한 구동력이 존재하지 않아 성장 구동력을 받는 모든 입자들이 성장하기 때문에 정상 입자 성장을 하게 된다. 이와 같이 입자 모양에 따른 입자 성장 거동은 전체 미세구조를 결정하게 되며, 이에 따른 물리 화학적 물성을 변화시킨다. 이러한 입자 성장 원리를 적용하 면 복합초경계 (TiCN-WC-Co)에서도 입자성장이 억제되고 치밀한 소결체를 제조할 수 있을 것이다. 본 실험에서는 평균입도가 각각 0.1, 1.33, 2$\mu\textrm{m}$인 TiCN, WC, Co 분말을 사용하여 $((I00_{-x)}TiCN+_xWC)-30Co$ (wt%) 조성에서 TiCN/WC 비를 변화시키면서 업자 모양과 입자성장 거동을 관찰하였다. 청량된 분말은 WC 초경 볼로 밀렁하고, 건조한 후, 100 mesh 체로 조립화 하였다. 이 분말을 100 MPa의 압력으로 냉간정수압성형 하고 $10^{-2}$ torr의 진공분위기의 graphite f furnace에서 carbon black으로 packing 하여 액상형성 온도 이상에서 소결하였다. 소결된 시편은 경면 연마하여 주사전자현미경으로 미세 조직을 관찰하였다. TiCN-30Co 조성 시편은 corner-round 모양의 입자 모양으로 소결 시간 증가에 따라 빠른 입자 성장을 나타내었다 .(7STiCN+2SWC)-30Co 조성 시변의 경우 일반적으로 보고된 바와 같이 core/shell 구조를 나타내었으며, core는 TiC-rich 상이었고, shell은 (Ti,W)(C,N) 복합 탄화물 상이었다. WC 함량이 중가함에 따라 입자의 corner-round 영역이 증가하였으며 (SOTiCN-SOWC)-30Co 조성 근처에서는 거의 둥근 형태의 입자 모양을 나타내었다. 또한 TiCN - 30Co 조성 시편에 비하여 WC가 첨가된 시펀들은 작은 평균입자크기를 나타내었다. 본 연구의 결과는 shell 영역 조성 변화는 계면에너지 이방성과 기지상 내의 펑형 입자 모양을 변화시키고 나아가 입자 성장 속도 에도 영향을 미친다는 것을 보여준다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.236-236
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• 2008

(Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

• Journal of the Microelectronics and Packaging Society
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• v.28 no.1
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• pp.39-46
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• 2021

The quantitative measurement of interfacial adhesion energy (Gc) of multilayer thin films for Cu interconnects was investigated using a double cantilever beam (DCB) and 4-point bending (4-PB) test. In the case of a sample with Ta diffusion barrier applied, all Gc values measured by the DCB and 4-PB tests were higher than 5 J/㎡, which is the minimum criterion for Cu/low-k integration without delamination. However, in the case of the Ta/Cu sample, measured Gc value of the DCB test was lower than 5 J/㎡. All Gc values measured by the 4-PB test were higher than those of the DCB test. Measured Gc values increase with increasing phase angle, that is, 4-PB test higher than DCB test due to increasing plastic energy dissipation and roughness-related shielding effects, which matches well interfacial fracture mechanics theory. As a result of the 4-PB test, Ta/Cu and Cu/Ta interfaces measured Gc values were higher than 5 J/㎡, suggesting that Ta is considered to be applicable as a diffusion barrier and a capping layer for Cu interconnects. The 4-PB test method is recommended for quantitative adhesion energy measurement of the Cu interconnect interface because the thermal stress due to the difference in coefficient of thermal expansion and the delamination due to chemical mechanical polishing have a large effect of the mixing mode including shear stress.