• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.141-141
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• 2009

Blue light-emitting diodes (LEDs), violet laser diodes 같은 광전소자들은 질화물 c-plane 기판위에 소자로 응용되어 이미 상품화 되어 왔다. 그러나 2족-질화물 재료들은 wurtzite 구조를 가지므로 c-plane에 평행한 자연적인 극성을 띌 뿐만 아니라 결정 내부 stress로 인한 압전현상 또한 나타나 큰 내부 전기장을 형성하게 된다. 이렇게 생성된 내부 전기장은 전자와 홀의 재결합 효율을 감소시키고 소자 응용 시 red-shift의 원인이 되곤 한다. 따라서 최근 들어 m-plane(1-100), a-plane (11-20)같은 무극성을 뛰는 기판 위에 소자를 만드는 방법이 각광을 받고 있는 추세다. 그러나 무극성 기판을 소자에 응용 시 Chemical Mechanical Planarization (CMP)에 의한 가공은 반도체 기판으로써 이용하기 위한 필수 불가결의 공정이다. c면(0001) SiC wafer에 대한 연구는 현재 많이 발표가 되어 있으나 무극성면 SiC wafer에 대한 CMP 공정에 대한 연구사례는 없는 실정이다. 본 연구에서는 C면 (0001)으로 성장된 잉곳을 a면(11-20)과 m(1-100)면으로 절단 후, slurry type (KOH-based colloidal silica slurry, NaOCl), 산화제, 연마제등을 변화하여 CMP 공정을 거침으로서 일어나는 기계 화학적 가공 양상에 대하여 알아보았다. 그 후 표면 형상 분석 하기위해 Atomic Force Microscope(AFM)을 사용하였고, 표면 스크레치를 SEM을 이용해서 알아보았다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.63-63
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• 2003

The nanotopography of silicon wafers has emerged as an important factor in the STI process since it affects the post-CMP thickness deviation (OTD) of dielectric films. Ceria slurry with surfactant is widely applied to STI-CMP as it offers high oxide-to-nitride removal selectivity. Aiming to control the nanotopography impact through ceria slurry characteristics, we examhed the effect of surfactant concentration and abrasive size on the nanotopography impact. The ceria slurries for this study were produced with cerium carbonate as the starting material. Four kinds of slurry with different size of abrasives were prepared through a mechanical treatment The averaged abrasive size for each slurry varied from 70 nm to 290 nm. An anionic organic surfactant was added with the concentration from 0 to 0.8 wt %. We prepared commercial 8 inch silicon wafers. Oxide Shu were deposited using the plasma-enhanced tetra-ethyl-ortho-silicate (PETEOS) method, The films on wafers were polished on a Strasbaugh 6EC. Film thickness before and after CMP was measured with a spectroscopic ellipsometer, ES4G (SOPRA). The nanotopogrphy height of the wafer was measured with an optical interferometer, NanoMapper (ADE Phase Shift)

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.3
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• pp.128-132
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• 2004

The perovskite ferroelectric materials of the PZT, SBT and BST series will attract much attention for application to ULSI devices. Among these materials, the BST ($Ba_0.6$$Sr_0.4$/$TiO_3$) is widely considered the most promising for use as an insulator in the capacitors of DRAMS beyond 1 Gbit and high density FRAMS. Especially, BST thin films have a good thermal-chemical stability, insulating effect and variety of Phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the surface characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.127-132
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• 2012

In this paper, the edge effects of proposed structure in active region for high voltage in shallow trench isolation for very large integrated MOSFET were simulated. Shallow trench isolation (STI) is a key process component in CMOS technologies because it provides electrical isolation between transistors and transistors. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• Journal of the Korea Society for Simulation
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• v.22 no.4
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• pp.93-98
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• 2013

In this paper, the proposed shallow trench isolation structures for high threshold voltage for very large scale and ultra high voltage integrated circuits MOSFET were simulated. Physically based models of hot-carrier stress and dielectric enhanced field of thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated devices over an extended range of stress biases and ambient temperatures. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1146-1150
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• 2009

Cadmium telluride (CdTe) is one of the most attractive photovoltaic materials due to its low cost, high efficiency and stable performance in physical, optical and electronic properties. Few researches on the influences of uniform surface on the photovoltaic characteristics in large-area CdTe solar cell were not reported. As the preceding study of the effects of thickness-uniformity on the photovoltaic characteristics for the large-area CdTe thin film solar cell, chemical mechanical polishing (CMP) process was investigated for an enhancement of thickness-uniformity. Removal rate of CdTe thin film was 3160 nm/min of the maximum value at the 200 $gf/cm^2$ of down force (pressure) and 60 rpm of table speed (velocity). The removal rate of CdTe thin film was more affected by the down force than the table speed which is the two main factors directly influencing on the removal rate in CMP process. RMS roughness and peak-to-valley roughness of CdTe thin film after CMP process were improved to 96.68% and 85.55%, respectively. The optimum process condition was estimated by 100 $gf/cm^2$ of down force and 60 rpm of table speed with the consideration of good removal uniformity about 5.0% as well as excellent surface roughness for the large-area CdTe solar cell.

• The Journal of Bigdata
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• v.4 no.2
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• pp.61-71
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• 2019

Chemical Mechanical Planarization (CMP) process that planarizes semiconductor wafer's surface by polishing is difficult to manage reliably since it is under various chemicals and physical machinery. In CMP process, Material Removal Rate (MRR) is often used for a quality indicator, and it is important to predict MRR in managing CMP process stably. In this study, we introduce prediction models using machine learning techniques of analyzing time-series sensor data collected in CMP process, and the classification models that are used to interpret process quality conditions. In addition, we find meaningful variables affecting process quality and explain process variables' conditions to keep process quality high by analyzing classification result.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.66-66
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• 2007

Lead zirconate titanate (PZT) is one of the most attractive perovskite-type materials for ferroelectric random access memory (FRAM) due to its higher remanant polarization and the ability to withstand higher coercive fields. We first applied the damascene process using chemical mechanical polishing (CMP) to fabricate the PZT thin film capacitor to solve the problems of plasma etching including low etching profile and ion charging. The $0.8{\times}0.8\;{\mu}m$ square patterns of silicon dioxide on Pt/Ti/$SiO_2$/Si substrate were coated by sol-gel method with the precursor solution of PZT. Damascene process by CMP was performed to pattern the PZT thin film with the vertical sidewall and no plasma damage. The polarization-voltage (P-V) characteristics of PZT capacitors and the current-voltage characteristics (I-V) were examined by change of process parameters. To examine the CMP induced damage to PZT capacitor, the domain structure of the polished PZT thin film was also investigated by piezoresponse force microscopy (PFM).

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.47-51
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• 2013

Chemical mechanical polishing (CMP) has become one of the key processes in wafer level stacking technology for 3D stacked IC. In this study, two-step CMP process was proposed to polish $Cu/SiO_2$ hybrid bonding surface, that is, Cu CMP was followed by $SiO_2$ CMP to minimize Cu dishing. As a result, Cu dishing was reduced down to $100{\sim}200{\AA}$ after $SiO_2$ CMP and surface roughness was also improved. The bonding interface showed no noticeable dishing or interface line, implying high bonding strength.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.213-217
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• 2007

Copper has been used as an interconnect material in the fabrication of semiconductor devices, because of its higher electrical conductivity and superior electro-migration resistance. Chemical mechanical polishing(CMP) technique is required to planarize the overburden Cu film in an interconnect process. Various problems such as dishing, erosion, and delamination are caused by the high pressure and chemical effects in the Cu CMP process. But these problems have to be solved for the fabrication of the next generation semiconductor devices. Therefore, new process which is electro-chemical mechanical polishing(ECMP) or electro-chemical mechanical planarization was introduced to solve the technical difficulties and problems in CMP process. In the ECMP process, Cu ions are dissolved electrochemically by the applying an anodic potential energy on the Cu surface in an electrolyte. And then, Cu complex layer are mechanically removed by the mechanical effects between pad and abrasive. This paper focuses on the manufacturing of ECMP system and its process. ECMP equipment which has better performance and stability was manufactured for the planarization process.