• Journal of Information Technology Services
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• v.1 no.1
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• pp.57-66
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• 2002

We are looking at the two different kinds of IT on this paper. One is VoIP and the other is VR (voice recognition). We are more interesting at the evolving techniques and services produced by combining the two techniques mentioned above. Recently, there are so many services and products appeared in the market using voice recognition technique. Now the technique has progressed on the level that can even replace the user interfaces using the QUI or general DTMF. Therefore, we are expecting so many various new services showed UP In the market which is combination of the VoIP and VR. Up until now, three models are available in the field which are wired telephone, wireless telephone, and wireless internet. We know the effectiveness of the VoIP is maximized more when this technique is combined with others rather than used alone without other techniques.

• Journal of the Korean Institute of Landscape Architecture
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• v.49 no.2
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• pp.1-16
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• 2021

The act of design in landscape architecture consists of a concept within a designer's mind, technical representations, and finally, a process of construction. In the 4th Industrial Revolution, the design process is facing many changes due to the rapid development of computer technology and the IT ecosystem. Computer technology was initially developed for simple functions, such as mathematical calculation and graphic representation. However, after the spread of Personal Computers, starting with IBM and Macintosh, programming languages and hardware rapidly developed, algorithms and applications became specialized, and the purpose of using computers became very diverse. This study diagnoses issues concerning the functions and roles that new design methods, such as computational design, parametric design, and algorithmic design, can play in landscape architecture based on changes in the digital society. The study focused on the design methodology using parametric technology, which has recently received the most attention. First, the basis for discussion was developed by examining the main concepts and characteristics of parametric design in modern landscape architecture. Prior research on the use of parametric design in landscape architecture was analyzed, as were the case studies conducted by landscape design firms. As a result, it was confirmed that parametric design has not been sufficiently discussed in terms of the number and diversity of studies compared to other techniques investigated by landscape design firms. Finally, based on the discussion, the study examined specific cases and future possibilities of the parametric design in landscape architecture.

• Convergence Security Journal
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• v.18 no.1
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• pp.117-128
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• 2018

The purpose of this paper is to analyze the behavior of North Korea's cyber attack against South Korea since 2009 based on major international security theories and suggest South Korea's policy option. For this purpose, this paper applied the behavioral domain and characteristics of 'cyber power' and 'coercion dynamics' model, which are attracting attention in international security studies. The types of cyber attacks from North Korea are classified into the following categories: power-based incarceration, leadership attacks and intrusions, military operations interference, and social anxiety and confusion. In terms of types and means of cyber power, North Korean GPS disturbance, the Ministry of Defense server hacking and EMP are hard power with high retaliation and threat and cyber money cashing and ransomware are analyzed by force in the act of persuasion and incentive in the point of robbing or asking for a large amount of money with software pawns. North Korea 's cyber attack has the character of escape from realistic sanctions based on the second nuclear test. It is important for South Korea to clearly recognize that the aggressive cyberpower of North Korea is changing in its methods and capabilities, and to ensure that North Korea's actions result in far greater losses than can be achieved. To do this, it is necessary to strengthen the cyber security and competence to simultaneously attack and defend through institutional supplement and new establishment such as cyber psychological warfare, EMP attack preparation, and enhancement of security expertise against hacking.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.5
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• pp.179-187
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• 2003

Recently efficient implementation of finite field operation has received a lot of attention. Among the GF($2^m$) arithmetic operations, multiplication process is the most basic and a critical operation that determines speed-up hardware. We propose a hardware architecture using Mastrovito method to reduce processing time. Existing Mastrovito multipliers using the special generating trinomial p($\chi$)=$x^m$+$x^n$+1 require $m^2$-1 XOR gates and $m^2$ AND gates. The proposed multiplier needs $m^2$ AND gates and $m^2$＋($n^2$-3n)/2 XOR gates that depend on the intermediate term xn. Time complexity of existing multipliers is $T_A$+( (m-2)/(m-n) +1+ log$_2$(m) ) $T_X$ and that of proposed method is $T_X$＋(1＋ log$_2$(m-1)＋ n/2 ) )$T_X$. The proposed architecture is efficient for the extension degree m suggested as standards: SEC2, ANSI X9.63. In average, XOR space complexity is increased to 1.18% but time complexity is reduced 9.036%.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.83-94
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• 2006

This paper describes ATM cell encipherment method using Rijndael Algorithm adopted as an AES(Advanced Encryption Standard) by NIST in 2001. ISO 9160 describes the requirement of physical layer data processing in encryption/decryption. For the description of ATM cell encipherment method, we implemented ATM data encipherment equipment which satisfies the requirements of ISO 9160, and verified the encipherment/decipherment processing at ATM STM-1 rate(155.52Mbps). The DES algorithm can process data in the block size of 64 bits and its key length is 64 bits, but the Rijndael algorithm can process data in the block size of 128 bits and the key length of 128, 192, or 256 bits selectively. So it is more flexible in high bit rate data processing and stronger in encription strength than DES. For tile real time encryption of high bit rate data stream. Rijndael algorithm was implemented in FPGA in this experiment. The boundary of serial UNI cell was detected by the CRC method, and in the case of user data cell the payload of 48 octets (384 bits) is converted in parallel and transferred to 3 Rijndael encipherment module in the block size of 128 bits individually. After completion of encryption, the header stored in buffer is attached to the enciphered payload and retransmitted in the format of cell. At the receiving end, the boundary of ceil is detected by the CRC method and the payload type is decided. n the payload type is the user data cell, the payload of the cell is transferred to the 3-Rijndael decryption module in the block sire of 128 bits for decryption of data. And in the case of maintenance cell, the payload is extracted without decryption processing.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.