• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.595-598
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• 2014

원전 디지털 계측제어시스템에서 공통원인고장(Common cause failure)의 발생 가능성이 증가함에 따라 이를 방지하기 위해 프로그래머블 논리소자(Field Programmable Gate Array)를 이용한 제어기가 개발되어 활용되고 있다. 그러나, FPGA-기반의 제어기를 구현하는데 사용되는 하드웨어 기술 언어는 그래픽 언어를 이용한 PLC 기반의 개발을 하던 대부분의 원전 계측제어 엔지니어에게 친숙하지 않아 제어기의 구현에 어려움이 있다. 따라서 엔지니어에게 친숙한 그래픽 언어를 이용하여 FPGA 용 제어 프로그램을 작성할 수 있는 통합개발환경이 필요하다. 본 논문에서 구현한 VerilogLinker 는 제어프로그램의 개발을 위한 통합개발환경의 일부로 통합개발환경을 이용한 제어 프로그램의 개발과정 중에서 생성된 Verilog 파일을 FPGA 공급자가 제공하는 상용 소프트웨어인 Libero SoC 와 연결하는 기능을 제공한다.

• Proceedings of the KSRS Conference
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• 2008.03a
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• pp.3-6
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• 2008

본 논문에서는 레일형 GB-SAR의 단점을 극복하고자 차량에 원형레일을 탑재하여 신속한 기동을 확보하고 합성구경의 길이를 늘리며 영상영역을 확장한 Arc-SAR의 설계안을 제시한다. 하드웨어 측면에서 살펴보면, 밴형 차량의 상부에 원형레일을 설치하고 마이크로파 송, 수신 안테나를 탑재한 후 레일 위를 1mm 이내의 정밀도로 이동시키며, 자료를 획득하게 된다. 이때 안테나에 연결된 동축 케이블은 차량 내부의 송, 수신장치에 연결되는데 RF대역에서 완벽히 작동하는 슬립링이 없기 때문에 내부 송, 수신 장치를 턴 테이블위에 장착하여 외부 안테나의 이동과 동일한 각도로 회전하여, 동축 케이블의 꼬임을 방지하게 된다. 송, 수신 장치의 구성은 벡터 네트워크 분석기를 기반으로 마이크로파 앰프, 마이크로파 스위치로 구성되며, 통합 제어 소프트웨어를 통해 외부 안테나의 이동과 함께 제어된다. 한편, Arc-SAR 영상의 구현은 원형레일을 따라 얻어지는 합성구경의 기하학적인 특수성을 감안하여 최초로 시도될 것이다. 이 시스템은 RTK-GPS를 장착하여 지반변형 모니터링 시 차량 이동 오차를 최소화 하고자 하며, 이외에 고정형 산란체를 이용하여 차량 이동 오차를 보정하고자 한다. 또한 AWS (Automatic Weather System)을 장착하여 위상의 대기보정을 동시에 수행할 것이다. 이 시스템은 차량 탑재에 의한 기동성의 확보로 침수나 침하 등 긴급 재난 지역에 즉각적인 대응이 가능하며, 대형 구조물의 주기적인 변형 모니터링 등에 활용성이 클 것이다.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.285-292
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• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2725-2730
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• 2012

In this paper, for improving the H.264/AVC hardware performance, we propose an inter predictor hardware design using a multi reference frame selector and an implicit weighted predictor. previous reference frame are reused for Low Memory Bandwidth. The size of the reference memory in the predictor was reduced by about 46% and the external memory access rate was reduced by about 24% compared with the one in the reference software JM16.0. We designed the proposed system with Verilog-HDL and synthesized inter predictor circuit using the Magnachip 0.18um CMOS standard cell library. The synthesis result shows that the gate count is about 2,061k and the design can run at 91MHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.2
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• pp.432-443
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• 2017

The primary goal of the MPEG-H 3D Audio standard is to provide immersive audio environments for high-resolution broadcasting services such as UHDTV. This standard incorporates a wide range of technologies such as encoding/decoding technology for multi-channel/object/scene-based signal, rendering technology for providing 3D audio in various playback environments, and post-processing technology. The reference software decoder of this standard is a structure combining several modules and can operate in various modes. Each module is composed of independent executable files and executed sequentially, real time decoding is impossible. In this paper, we make DLL library of the core decoder, format converter, object renderer, and binaural renderer of the standard and integrate them to enable frame-based decoding. In addition, by measuring the computation complexity of each mode of the MPEG-H 3D-Audio decoder, this paper also provides a reference for selecting the appropriate decoding mode for various hardware platforms. As a result of the computational complexity measurement, the low complexity profiles included in Korean broadcasting standard has a computation complexity of 2.8 times to 12.4 times that of the QMF synthesis operation in case of rendering as a channel signals, and it has a computation complexity of 4.1 times to 15.3 times of the QMF synthesis operation in case of rendering as a binaural signals.

• The KIPS Transactions:PartD
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• v.12D no.7 s.103
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• pp.1049-1064
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• 2005

The demands of increasingly complicated software have led to the proliferation of object-oriented design methodologies in embedded systems. To execute a system designed with objects in target hardware, a task set should be derived from the objects, representing how many tasks reside in the system and which task processes which event arriving at an object. The derived task set greatly influences the responsiveness of the system. Nevertheless, it is very difficult to derive an optimal task set due to the discrepancy between objects and tasks. Therefore, the common method currently used by developers is to repetitively try various task sets. This paper proposes Scenario-based Implementation Synthesis Architecture (SISA) to solve this problem. SISA encompasses a method for deriving a task set from a system designed with objects as well as its supporting development tools and run-time system architecture. A system designed with SISA not only consists of the smallest possible number of tasks, but also guarantees that the response time for each event in the system is minimized. We have fully implemented SISA by extending the ResoRT development tool and applied it to an existing industrial PBX system. The experimental results show that maximum response times were reduced $30.3\%$ on average compared to when the task set was derived by the best known existing methods.