• Title/Summary/Keyword: 하드웨어 구조

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Digital Logic Extraction from QCA Designs (QCA 설계에서 디지털 논리 자동 추출)

  • Oh, Youn-Bo;Kim, Kyo-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.1
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    • pp.107-116
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    • 2009
  • Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

Efficient Algorithms for Motion Parameter Estimation in Object-Oriented Analysis-Synthesis Coding (객체지향 분석-함성 부호화를 위한 효율적 움직임 파라미터 추정 알고리듬)

  • Lee Chang Bum;Park Rae-Hong
    • The KIPS Transactions:PartB
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    • v.11B no.6
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    • pp.653-660
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    • 2004
  • Object-oriented analysis-synthesis coding (OOASC) subdivides each image of a sequence into a number of moving objects and estimates and compensates the motion of each object. It employs a motion parameter technique for estimating motion information of each object. The motion parameter technique employing gradient operators requires a high computational load. The main objective of this paper is to present efficient motion parameter estimation techniques using the hierarchical structure in object-oriented analysis-synthesis coding. In order to achieve this goal, this paper proposes two algorithms : hybrid motion parameter estimation method (HMPEM) and adaptive motion parameter estimation method (AMPEM) using the hierarchical structure. HMPEM uses the proposed hierarchical structure, in which six or eight motion parameters are estimated by a parameter verification process in a low-resolution image, whose size is equal to one fourth of that of an original image. AMPEM uses the same hierarchical structure with the motion detection criterion that measures the amount of motion based on the temporal co-occurrence matrices for adaptive estimation of the motion parameters. This method is fast and easily implemented using parallel processing techniques. Theoretical analysis and computer simulation show that the peak signal to noise ratio (PSNR) of the image reconstructed by the proposed method lies between those of images reconstructed by the conventional 6- and 8-parameter estimation methods with a greatly reduced computational load by a factor of about four.

Redesign Application Architecture for Advanced Volcanic Disaster Response System (화산재해대응시스템 고도화를 위한 응용아키텍처 재설계)

  • Youn, Junhee;Kim, Tae-Hoon;Kim, Dusik
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.19 no.3
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    • pp.90-95
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    • 2018
  • The Korean Peninsula is no longer safe from volcanic disasters. Therefore, the Korean government has been developing a spatial information-based system implementation technology since 2014. VDRS (Volcanic Disaster Response System), which is the result of the technology, was implemented in 2016 as Phase I. Since then, phase II implementation technology has been developed for an advanced system reflecting the user's requirements. To advance the system, redesign architecture is essential. This paper examined the redesign application architecture for an advanced VDRS. First, existing application architecture, which was implemented in phase I, was analyzed. Second, the user's requirements for advanced VDRS were analyzed. The analyzed user's requirements were categorized as a transforming service oriented to a business-oriented architecture, improving accuracy, and expanding the spatial range and target disaster. Third, application architecture was redesigned based on gap analysis between the existing architecture and user's requirements. The results of the proposed redesign architecture are presented as the application system structure and description of the application function based on owner's point of view in the enterprise architecture. The results of this paper can be used to derive the application module design and provide a detailed description of the application module based on the designer's point of view. Further research focused on structuring the HW/SW architecture will be required for system implementation.

A Novel Distributed Secret Key Extraction Technique for Wireless Network (무선 네트워크를 위한 분산형 비밀 키 추출 방식)

  • Im, Sanghun;Jeon, Hyungsuk;Ha, Jeongseok
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39A no.12
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    • pp.708-717
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    • 2014
  • In this paper, we present a secret key distribution protocol without resorting to a key management infrastructure targeting at providing a low-complexity distributed solution to wireless network. The proposed scheme extracts a secret key from the random fluctuation of wireless channels. By exploiting time division duplexing transmission, two legitimate users, Alice and Bob can have highly correlated channel gains due to channel reciprocity, and a pair of random bit sequences can be generated by quantizing the channel gains. We propose a novel adaptive quantization scheme that adjusts quantization thresholds according to channel variations and reduces the mismatch probability between generated bit sequences by Alice and Bob. BCH codes, as a low-complexity and pratical approach, are also employed to correct the mismatches between the pair of bit sequences and produce a secret key shared by Alice and Bob. To maximize the secret key extraction rate, the parameters, quantization levels and code rates of BCH codes are jointly optimized.

The computer-Integrated Business System(CIBS) for Highly Decentralized Organizations (분산조직을 위한 컴퓨터 통합 비즈니스 시스템)

  • 박광호;권용균
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 1996.10a
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    • pp.153-156
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    • 1996
  • 현재의 정보시스템이 하드웨어의 발전에 비해 늦어진 이유는 개발 단계별로 상호 일관성이 결여된 방법론을 사용하고 있고 이 방법론들이 실제의 비즈니스 프로세스(Business Process)와는 차이가 있는 형태로 구현이 되기 때문이다. 또한, 이런 방법론들이 분산조직에 사용된다면 비즈니스 프로세스가 세분화되기 때문에 문제점들이 더 깊이 심화되는 경향이 발생하게 된다. 이런 상황에 대한 해결책은 정보시스템이 비즈니스 프로세스로부터 구체적인 정보시스템의 구현에 이르기까지 일관성 있게 진행할 수 있는 방법론이 필요하다. 그러므로, 정보시스템 구현의 각 단계별로 추상과 구현방법을 구체적으로 제시하고 개념적인 무결성을 보장할수 있는 새로운 정보시스템 개발방법이 요구된다. 본 논문에서는 이러한 정보시스템을 구현하기 위해서 업무분석의 과정에서부터 구현에 이르기까지 개념적인 무결성(Conceptual Integrity)을 유지하고(Brooks, 1982) 방법론상에서 중단이나 변형없이 연결되는 시스템 개발방법론인 컴퓨터 통합 비즈니스 시스템(Computer-Integrated Business System:CIBS)을 소개하고 이 CIBS가 사용하는 세부적인 객체지향 프로그래밍 방법론이 AF(Application Framework)을 설명하며, 최종적으로 이 CIBS에 의해서 구현된 정보시스템과 기존의 프로그래밍 기법으로 구현된 정보시스템과의 비교를 통해 그 장단점을 증명하고자 한다. 또한, 이 CIBS구조는 정보시스템의 단편적인 정보제공 능력을 넘어서서 비즈니스 프로세스를 개선함에 의해서 기업의 노하우를 정립하고 이를 발전시키는 정보시스템의 진보된 형태를 보여줌으로서 정보시스템의 새로운 모습과 비젼을 제시하며 혁신적인 정보시스템의 새로운 구조를 보여준다. 문제점들은 HED (Human Engineerign Discrepance) 목록으로 정리하여 설계에 반영하도록 하였다.로 마음의 안정감, 몸의 긴장 이완에 따른 건강 상태 유지, 수업 집중도 향상 등이 나타났다. 위와 같은 종합 적 분석 결과에 따라, 본 연구는 제조 현장의 생산성 향상 및 품질 향상과 연계하여 작업자의 작업 집중도 향상, 작업자의 육체적, 심리적 변화에 따른 생산성 및 품질 향상 변화 정도 등의 산업공학(인간공학) 제 분야의 여러 측면에서 연구 및 적용이 가능하리라 사료된다.l, 시험군:25.90$\pm$7.16mg/d1, 47% 감소)를 나타내었으며, 시험군의 AUC는 대조군에 비해 39% 감소하였고, 혈중 아세트알데히드의 농도는 투여 60분후 시험군(3.96$\pm$0.07nmo1/$m\ell$)이 대조군(6.45$\pm$0,64nmo1/$m\ell$)에 비해 유의성 있는 감소(39%)를 나타내었으며, 시험군의 AUC는 대조군에 비해 48% 감소하였다 한편, 시험관내 에탄올 대사 효소에 대한 바이오짐의 효과를 검색해본 결과 바이오짐(2.0 $\mu\textrm{g}$/assay)에 의해 Aldehyde dehydrogenase(1.5unit/assay)의 활성이 14% 증가되었다. 본 연구의 결과로 볼 때, 비지니스 및 바이오짐은 음주 후 상승된 혈중 에탄을 농도 및 아세트알데히드의 농도를 현저히 감소시키는 효과가 있었다.량 보호 관리, 도시 소공원 개발, 역사 문화 공원 조성, 하천 공간 복원, 공원 시설 기능 개선, 이용 프로그램 개발, 공원 관리 개선, 환경 피해 녹지의 회복, 도시 환경 림 조성, 녹지 기능

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An Emulation System for Efficient Verification of ASIC Design (ASIC 설계의 효과적인 검증을 위한 에뮬레이션 시스템)

  • 유광기;정정화
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.10
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    • pp.17-28
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    • 1999
  • In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

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Community Business and Regional Development: A Case Study of Sungmisan Village in Mapo-Gu, Seoul (커뮤니티 비즈니스와 지역발전 -서울특별시 마포구 성미산 마을을 사례로-)

  • Lee, Hongtaek;Jung, Sung-Hoon
    • Journal of the Economic Geographical Society of Korea
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    • v.15 no.4
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    • pp.708-720
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    • 2012
  • The main aim of paper is to analyse relationships of objects, methods and main agents for the sustainable growth of community business (CB). Since the 1990s, Korea central-local governments have carried out a variety of policies to revitalize the rural economy, but many policies did not work effectively. The main reason for this is that those policies were simply focused on construct the hardware-based infrastructure without considerations of community capabilities. Recently, to overcome these problems, various kinds of community business policies are carried out across the country. Therefore, to avoid previous problems, the concrete and thorough analysis on the current CB has to be required. To do this analysis, four case studies on Sungmisan Village (in Mapo-Gu, Seoul) were taken and analysed in this paper. Results for this are as follows; Firstly, for the sustained growth of CB, it has to be required that the needs and demands of communities and residents are reflected. In the case of Sungmisan CB, residents were relatively satisfied with their community products, even though tastes and prices of those products were not very attractive. The reason for this is that those products were created by needs of local people. In this process, a market within the village was created and the basis of the management was established. Secondly, in order to secure a stable profit's structure that is necessary at the early stage of business settlement, creating related networks with Sungmisan CB is necessary. The CB established a stable profit structure by using mutual commodities. In particular, they linked closely and mutually so that visitors can buy their commodities. Lastly, for the sustainable management of the CB a common target local people should be set up. Furthermore, a system for income distribution has to be needed for protecting and solving potential conflicts.

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MPEG-H 3D Audio Decoder Structure and Complexity Analysis (MPEG-H 3D 오디오 표준 복호화기 구조 및 연산량 분석)

  • Moon, Hyeongi;Park, Young-cheol;Lee, Yong Ju;Whang, Young-soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.42 no.2
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    • pp.432-443
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    • 2017
  • The primary goal of the MPEG-H 3D Audio standard is to provide immersive audio environments for high-resolution broadcasting services such as UHDTV. This standard incorporates a wide range of technologies such as encoding/decoding technology for multi-channel/object/scene-based signal, rendering technology for providing 3D audio in various playback environments, and post-processing technology. The reference software decoder of this standard is a structure combining several modules and can operate in various modes. Each module is composed of independent executable files and executed sequentially, real time decoding is impossible. In this paper, we make DLL library of the core decoder, format converter, object renderer, and binaural renderer of the standard and integrate them to enable frame-based decoding. In addition, by measuring the computation complexity of each mode of the MPEG-H 3D-Audio decoder, this paper also provides a reference for selecting the appropriate decoding mode for various hardware platforms. As a result of the computational complexity measurement, the low complexity profiles included in Korean broadcasting standard has a computation complexity of 2.8 times to 12.4 times that of the QMF synthesis operation in case of rendering as a channel signals, and it has a computation complexity of 4.1 times to 15.3 times of the QMF synthesis operation in case of rendering as a binaural signals.

A Performance Analysis of DF-DPD and DPD-RGPR (DF-DPD와 DPD-RGPR에 대한 성능 분석)

  • Jeong, Jin-Doo;Jin, Yong-Sun;Chong, Jong-Wha
    • 전자공학회논문지 IE
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    • v.47 no.4
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    • pp.39-47
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    • 2010
  • This paper proposes a numerical analysis to prove that the performance of the differential phase detections (DPDs) with the decision feedback, such as the decision feedback DPD (DF-DPD) and the DPD with recursively generated phase reference (DPD-RGPR), approach the performance of the coherent detection with differential decoding. The conventional differential phase detection for M-ary DPSK can make the receiver architecture simple, while it can make the bit-error rate (BER) performance poor because of the previous noisy phase as a reference phase. To improve the BER performance of the conventional differential detection, multiple symbol differential detection methods, including DF-DPD and DPD-RGPR, have been proposed. However, the studies on the analysis and on the comparison of these methods have been little performed. Then, this paper mathematically intends to analyze and compare the performance of the DPDs with the decision feedback. The analysis results show that the DPDs with the decision feedback can have the performance equal to that of the coherent detection with differential decoding and be available for the noncoherent detection in the improved performance. Considering the hardware complexity, the DPD RGPR with the simple detection process by using the recursively generated phase reference can be more simply implemented than the DF-DPD based on the architecture whose complexity increases according to the increasing detection length.

An Implementation of Low Power MAC using Improvement of Multiply/Subtract Operation Method and PTL Circuit Design Methodology (승/감산 연산방법의 개선 및 PTL회로설계 기법을 이용한 저전력 MAC의 구현)

  • Sim, Gi-Hak;O, Ik-Gyun;Hong, Sang-Min;Yu, Beom-Seon;Lee, Gi-Yeong;Jo, Tae-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.4
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    • pp.60-70
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    • 2000
  • An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4:2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

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