• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.1
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• pp.54-62
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• 1995

This paper is a study on a speed control of an induction motor used the MRA-DSM(Mode1 Reference Adaptive-Discrete Sliding Mode) controller. In this paper, when controls motor speed, DSM algorithm is proposed for having Robustness against disturbance and parameter variation. and it is also proposed MRA-DSM including the additional load model reference algorithm, which can be compensated the discontinuous control imputs at sliding mode and followed the model Preference independent of parameter variation of control subjects. The control system is composed of the parallel processing control system using the microprocessor for maximizing the performance of control systems and the real time processing. Also it simplifies the hardware composed of controlling the system by software and improves the reliability of the system. And while MRA-DSM control, faster response characteristics of 27.2 % is obtained than DSM control.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.754-766
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• 2010

In the wireless communication protocols, a network device is responsible for the operation of lower-layers. The network device consists of hardware and software modules, so it can be designed using system-on-chip simulator. The simulator design needs the support of a network simulator as well as system-on-chip simulator, because the network device interact with various higher layer communication protocols. Therefore the co-simulator can become a development environment of the network device through the combining of them. In this paper we propose a co-simulator combining these two simulators. The proposed co-simulator does not degrade performance due to integrations. Also, it is easy to integrate them because the implementation of the kernel is independent.

• Journal of Energy Engineering
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• v.5 no.2
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• pp.153-159
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• 1996

The Sequence Of Event (SOE) system used in nuclear power plants is a part of the Plant Data Acquisition System (PDAS). The SOE system of the existing nuclear power plant shares the computer H/W and S/W with PDAS, and requires more complicated structure using three processors to provide the events or trip signals. Moreover, there are high potential of collision between synchronization signals and data transmitted to the Plant Computer System (PCS) when the synchronization signals are sent from PCS to the three SOE processors. When this collision happens the SOE system will break down, thus it is not possible to analyze the trend of events or trips. This paper issues the limitations item of the existing SOE system and proposes the novel SOE system using single processor. And the test system for proposed SOE system is designed, implemented and tested.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.194-204
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• 2003

The performance of a shared memory multiprocessor system is dependent on the system software such as scheduling policy as well as hardware system. Most of existing simulators, however, do not support simulation for multi-programmed environment because they can execute only a single benchmark application at a time. We propose a multi-programmed simulation method on a program-driven simulator, which enables the concurrent executions of multiple parallel workloads contending for limited system resources. Using the proposed method, system developers can measure and analyze detailed effects of resource conflicts among the concurrent applications as well as the effects of scheduling policies on a program-driven simulator. As a result, the proposed multi-programmed simulation provides more accurate and realistic performance projection to design a multiprocessor system.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.167-173
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• 2015

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.427-430
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• 2012

최근 차량용 블랙박스, 자동 운전 시스템, 어라운드 뷰 시스템 등과 같은 운전자의 편의와 안전을 위한 장치 및 시스템들이 개발되고 있다. 현재 운전자를 위한 보조 시스템으로 구글(google)의 자동 운전 시스템(Auto Car Driving System)과 현대 모비스(hyundai mobis)의 AVM 시스템(Around View Monitoring System) 등의 다양한 차량용 편의장치 시스템들이 등장했다. 위와 같은 다양한 ECU들을 관리하기 위한 서버 및 저장 장치 역할을 할 수 있는 고사양의 Car PC의 장착이 필수적이다. 기존의 AVM 시스템은 차량 주변을 실시간으로 제공하기 위해 임베디드 또는 별도의 차량용 네트워크를 통해 임베디드 시스템 또는 SoC(System On Chip)형태의 하드웨어 기반으로 개발되고 있다. 하지만 고사양의 Car PC 기반에서는 별도의 비용없이 소프트웨어로 구현이 가능하다. 본 논문에서는 차량의 전 후 좌 우에 장착된 4대의 카메라로부터 입력된 차량 주변 상황을 한눈에 보여주는 AVM 시스템(Around-View Monitoring System)을 위한 카메라 보정 및 정합 처리 모듈 및 AVM 시스템을 Windows를 O/S로 하는 PC 내부에서 기존의 AVM 시스템을 이용하여 화면에 전 후 좌 우 버튼을 각각 만들어 버튼을 터치했을 때, 각 버튼에 해당되는 영상이 AVM 시스템과 함께 출력되도록 하거나 디스플레이에 Full 버전으로 출력되도록 S-UI(Smart User Interface)를 설계 및 구현한다. 제안하는 AVM 시스템과 기존의 AVM 시스템의 성능과 기능을 비교 분석함으로써 제안하는 영상 처리 모듈을 이용하여 추가 비용이 발생하지 않는 AVM 시스템의 구현 가능성을 검증한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.109-112
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• 2005

배관에 생기는 구멍이나 틈은 대형 사고의 원인이 될 수 있다. 이러한 배관의 결함을 찾기 위해서는 먼저 센서를 부착한 배관 탐사 장비를 배관에 통과시키고, 배관을 통과하는 중에 센서가 읽은 정보들을 배관 탐사 장비의 하드 디스크에 저장한다. 배관 통과가 완료된 후, 분석가는 분석 프로그램을 사용하여 탐사 장비에서 얻은 데이터에서 결함을 수동적으로 찾는다. 분석가가 데이터를 분석할 때 일반적으로 두 가지 패턴이 존재한다. 첫 번째 패턴은 일정한 구간의 센서 데이터를 순차적으로 분석하는 패턴이고, 두 번째 패턴은 현재 구간에서 이전 구간으로 되돌아가서 다시 분석하는 반복적인 패턴이다. 현재까지 만족할 만 한 수준으로 자동적으로 분석이 되지 않으므로, 분석가는 수작업으로 분석을 하는 경우가 많은데 이로 인해 최근에 읽은 부분을 전후 반복해서 액세스하는 반복적인 패턴이 많이 사용된다. 반복적 패턴의 경우 시스템의 성능을 향상시키기 위해, 이전에 읽은 배관 센서 데이터를 캐싱 할 필요가 있다. 그러나 기존의 분석 소프트웨어에는 캐싱 기능이 없으므로 반복적 패턴일 경우 데이터베이스에서 동일한 데이터를 반복적으로 읽는 문제를 가지고 있다. 본 논문에서는 배관 센서 데이터를 효율적으로 관리하는 캐쉬 관리자를 설계하고 구현하였다. 세부적으로는, 배관 센서 데이터를 시계열 데이터로 간주하고, 시계열 데이터에 대한 캐시 관리자를 제안하였다. 본 논문은 배관 탐사 장비에서 획득한 데이터들을 시계열 데이터로 간주하여 데이터베이스 측면에서 이러한 문제들을 접근하였다는 점에서 의미가 있으며, 향후 이 분야에 대한 많은 연구들이 나올 것으로 기대한다.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.169-176
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• 2010

Nonstationary power quality(PQ) signals which the Sag, Swell, Impulsive Transients, and Harmonics make sometimes the operations of the industrial power electronics equipment, speed and motion controller, plant process control systems in the undesired environments. So, this PQ problem might be critical issues between power suppliers and consumers. Therefore, We have studied the PQ recognition system in order to acquire, analyze, and recognize the PQ signals using the software, i.e, MATLAB, Simulink, and CCS, and the hardware. i.e., TMS320C6713DSK(TI), The algorithms of the PQ recognition system in the Wavelet transforms and Backpropagation algorithms of the neural networks. Also, in order to verify the real-time performances of the PQ recognition system under the environments of software and hardware systems, SIL(Software In the Loop) and PIL(Processor In the Loop) were carried out, resulting in the excellent recognition performances of average 99%.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.201-208
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• 2008

An active RFID system has the advantages of a long identification distance and a good identification rate as well as overcoming the passive RFID's drawback such as the lowering of identification rate on metal materials. So, the development of an active RFID system has been gradually increasing in harbor logistics and the national defense area. On the other hand, some identification failures between products developed under the same standards have been reported, and there are difficulties in evaluating the interoperability between developed Products and standard conformance test because an accurate evaluation method and equipment has not been established at the international level. Motivated by these, this study presents a realization of the hardware and software of emulator to evaluate the standard conformance of an active RFID system, Performance of the designed system are then analyzed by means of simulations of Matlab/Simulink, and the applicability of the emulator is verified by evaluating the standard conformance of a real active RFID tag.