• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.2
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• pp.17-22
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• 2012

This paper deals with a precoder design method when the system has imperfect channel information. When MIMO relay system knows the correlation coefficient between perfect channel and imperfect channel information and the variance of the difference between perfect channel and correlated imperfect channel, source and relay precoders are designed to maximize the upper bound of the channel capacity. Also, we investigate channel capacities of the system using proposed precoder and compare with the optimal value according to the correlation and the variance of error channel by simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.10
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• pp.921-928
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• 2012

In this paper, we propose a novel interference alignment transceiver for multi-cell MIMO downlink channels with arbitrary number of cells and users per cell. We design the receive beamformer to align the interference from undesired base stations to the effective inter-cell interference (ICI) channels. Subsequently, we design the transmit precoder which can nulllify the interference from the corresponding base station. The proposed transceiver design can attain the degrees of freedom (DOF) equal to the number of streams per user. Accordingly, we investigate conditions for the antenna configuration. From numerical results, we confirm that the proposed transceiver design can achieve higher DOF than the conventional scheme under equal antenna configuration.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.10
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• pp.879-882
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• 2021

The telemetry standard adopts SOQPSK-TG with excellent power and bandwidth efficiency as a modulation technique, and LDPC code with excellent performance as an error correction code. The SOQPSK-TG transmitter consists of a precoder and a CPM modulator. Rather than implementing each receiver separately, the reception performance is improved by combining the trellis and implementing it as a Viterbi decoder. In this paper, the reception performance of LDPC-encoded SOQPSK-TG was evaluated by replacing the Viterbi decoder with a max-log-map decoder capable of soft metric output. As a result of computer simulation in AWGN channel, there is an Eb/No performance gain of about more than 0.7~0.8dB compared to the conventional method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1903-1913
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• 2016

In this paper, we propose 2-stage beamformer with linear receiver in wireless backhaul downlink system where macro base station has large antenna array with sub-array structure. Also, to compare the system capacity, we apply 3-stage beamformer with zero-forcing precoder and calculate the achievable sum rate of received small cell base stations. Considering scattering and path-loss property of wireless backhaul channel, we combine precoding technique for spatial multiplexing and beamforming technique to overcome path-loss. Therefore, we design DFT-based fixed beam patterns for the first stage. The simulation results show that considering spatial multiplexing, proposed 2-stage beamformer with linear receiver can increase the achievable sum rate as well as reduce the feedback information.

• Journal of Advanced Marine Engineering and Technology
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• v.39 no.3
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• pp.280-285
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• 2015

We consider a linear transceiver design method for multi-user multiple-input multiple-output (MIMO) downlink channels where a base station (BS) equipped with a finitely large number of antennas. Although a matched-filter precoder is a capacity-achieving method in massive MIMO downlink systems, it cannot guarantee to achieve the multi-user MIMO capacity in a finitely large number of antennas due to inter-user interferences. In this paper, we propose a two-stage precoder design method that maximizes the sum-rate of cell-edge users when the BS equipped with a finitely large number of antennas. At the first stage, a matched-filter precoder is adopted to exploit both beamforming gain and the reduction of the dimension of effective channels. Then, we derive the second stage precoder that maximizes the sum-rate by minimizing the weighted mean square error (WMSE). From simulation and analysis, we verify the effectiveness of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7C
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• pp.611-617
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• 2010

In this paper, we investigate the performances of the serial concatenated convolutional codes (SCCC) and low-density parity-check (LDPC) codes on perpendicular magnetic recording (PMR) channels. We discuss the performance of two systems when user bit-densities are 1.7, 2.0, 2.4 and 2.8, respectively. The SCCC system is less complex than LDPC system. The SCCC system consists of recursive systematic convolutional (RSC) codes encoder/decoder, precoder and random interleaver. The decoding algorithm of the SCCC system is the soft message-passing algorithm and the decoding algorithm of the LDPC system is the log domain sum-product algorithm (SPA). When we apply the iterative decoding between channel detector and the error control codes (ECC) decoder, the SCCC system is compatible with the LDPC system even at the high user bit density.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.35-41
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• 2000

This paper considers the consturction of 24/25 I-NRZI (Interleaved - Non Return to Zero Inverse) modulator designs for DVCR (Digital Video Cassette Recorder), and size of validity bit in order to store the amplitude value of square-wave and the standard data ( sine and cosine coefficients) at ROM Table that to acceptable the spectrum standard. The validity bit size of the standard data and the amplitude value of square-wave that to store at ROM Table are affected the size of pilot signal on the output spectrum, and the hardware size of modulator. At the designable 24/25 I-NRZI modulator, we simulated using random pattern (F0,F1,F2) that to verification the output data of the spectrum. Moreover, the resultant of the spectrum analysis, at the optimizing value, is 0.065 on the amplitude value of square-wave, and 3bit on the size of bit in order to store the standared data at ROM Table. In order to verify the hardware of designable 24/25 I-NRZI modulator, we perform to modeling of C-language firstly, and coding to Verilog HDL (Cadence Verilog XL) and synthesized using Synopsys (Library "Samsung KG75") tool as a base of spectrum results. In a foundation of this result, we are considered the size of hardware. In this paper, a considerable 24/25 I-NRZI modulator designable less than 10,000 gates as that is improved consturction as regards the path method of pre-coder etc, and able to application digital camcorders as now practical use.