• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.270-273
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• 2012

In this paper, I present the design of Operational Flight Programs(OFPs) on a Multi-Core based Mission Computer(MC) for the optimized performance of the OFPs on Multi-Core based MC. The program assigned as tasks on Multi-Core environment can be scheduled by designing with the use of OpenMp, which is the standard for parallel programming. This paper also describes the differences between Multi-Core Program(MCP) on the technique and Single-Core Program(SCP) in terms of performance aspect. The new proposed design technique is applied to the Integrated Up-Front Control OFP(IUFC OFP) on General Processor Module where Multi-Core based. This paper describes the Multi-Core design technique for the optimized performance of the IUFC OFP, which display and control flight data(Navigation, Communication, Identification Friend or Foe) to pilot.

• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1478-1490
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• 2011

Recently, multi-core processors have been drawing significant interest from the embedded systems research and industry communities due mainly to their potential for achieving high performance and fault-tolerance at low cost in such products as automobiles and cell phones. To process multimedia data, a scheduling algorithm is required to meet timing constraints of periodic tasks in the system. Though Pfair scheduling algorithm can meet all the timing constraints while achieving 100% utilization on multi-core based system theoretically, however, the algorithm incurs high scheduling overheads including frequent core migrations and system-wide synchronizations. To mitigate the problems, we propose a real-time scheduling algorithm for multi-core based system so that system-wide scheduling is performed only when it is absolutely necessary. Otherwise the proposed algorithm performs scheduling within each core independently. The experimental results by extensive simulations show that the proposed algorithm dramatically reduces the scheduling overheads up to as negligible one when the utilization is under 80%.

• Journal of IKEEE
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• v.24 no.4
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• pp.1172-1175
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• 2020

Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.592-607
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• 2006

This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.252-255
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• 2010

고해상도의 동영상 서비스가 보편화 되면서 동영상을 빠르게 처리를 위한 연구가 활발히 이루어 지고 있다. 그리고 멀티코어 프로세서의 사용이 증가 하고 멀티코어 시스템에서 H.264/AVC 디코더를 구현하기 위하여 다양한 병렬화 방법이 제안되고 있다. 하지만 H.264/AVC디코더의 병렬화를 진행하는 과정에서 각 스레드에서 처리하는 데이터의 처리시간 차이로 인하여 스레드의 동기를 확인 해야 한다. 이로 인하여 병렬화를 통한 성능 향상의 걸림돌이 된다. 우리는 이러한 병렬화 과정에서 발생하는 문제점을 고려하여 효과적으로 H.264/AVC 디코더를 병렬화 하는 방법에 대하여 연구하였다. 우리가 제안하는 Frame Partition based Parallelization (FPP) 방법은 프레임을 매크로 블록 묶음으로 나누어 병렬화 한다. 그리고 병렬화 과정에서 스레드를 처리하는 방법을 개선하여 성능을 향상 시켰다. 본 논문에서는 FFmpeg H.264/AVC 디코더를 이용하여 실험 하였고 인텔 쿼드 코어 기반의 멀티코어 시스템에서 멀티 스레드로 구현하였다. 우리는 FPP 방법을 적용하여 병렬화 방법 적용 전 H.264/AVC 디코더와 비교하여 최대 53%의 성능 향상을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.232-234
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• 2017

In this research, the BLDC motor 2 axis controller was designed using a dual core processor. The controller used TMS320F28377D which is TI's latest dual-core DSP, and the BLDC motor was selected with the position of resolver having high reliavility and the speed sensor built-in type motor.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.412-417
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• 2007

멀티 포트 네트워크 인터페이스 카드는 지원 가능한 대역폭의 합이 포트의 수에 따라서 결정된다. 따라서 I/O 버스와의 대역폭 균형을 맞출 수 있는 장점이 있다. 또한 상대적으로 저렴한 스위치 가격으로 높은 대역폭을 지원해 줄 수 있다. 이러한 이유에서 최근 멀티 포트 네트워크 인터페이스 카드는 고 가용성 서버뿐만 아니라 고성능 서버에서도 사용되기 시작하고 있다. 본 논문에서는 이러한 멀티 포트 네트워크 인터페이스 카드가 지원할 수 있는 최대 대역폭을 분석한다. 특히 최근에 등장한 멀티 코어 프로세서 서버에서 TCP/IP 성능 측정을 수행하여 멀티 코어 자원을 최대한 활용하는지를 분석한다. 분석 결과 현재 리눅스가 제공하는 인터럽트 분산 정책 및 패킷 처리 기법으로는 멀티 포트 네트워크 인터페이스 카드의 높은 대역폭 특성을 최대한 활용하기에는 부족함을 밝힌다. 또한 각 포트 별로 들어오는 네트워크 흐름의 특성이 서로 다를 때에 시스템이 그에 신속히 적응하지 못함을 측정 결과를 통해서 보인다. 이러한 측정 및 분석 결과는 멀티 코어 시스템에서 멀티 포트 NIC을 최대한 활용하기 위한 리눅스의 향상 필요성을 시사하며 그를 위한 방안을 제시할 수 있다.

• Journal of KIISE
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• v.42 no.5
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• pp.551-557
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• 2015

The technology using ARM TrustZone draws attention as a new embedded virtualization approach. The ARM TrustZone defines two virtual execution environment, the secure world and the normal world. In such an environment, the inter-world communication is important to extend function of software. However, the current monitor software does not sufficiently support the inter-world communication. This paper presents a new inter guestOS communication scheme, for each world, for the ARM TrustZone virtualization. The proposed communication scheme supports bidirectional inter-world communication for single core and multicore environment. In this paper, It is implemented on a NVIDIA Tegra3 processor based on the ARM Cortex-A9 MPCore and it showed a bandwidth of 30MB/s.

• The Journal of the Acoustical Society of Korea
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• v.36 no.6
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• pp.425-435
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• 2017

In this paper, we propose optimization methods for speeding the feedforward network of deep neural networks using NEON SIMD (Single Instruction Multiple Data) parallel instructions and multi-core parallelization on the multi-core ARM processor. As the result of the optimization using SIMD parallel instructions, we present the amount of speed improvement and arithmetic precision stage by stage. Through the optimization using SIMD parallel instructions on the single core, we obtain $2.6{\times}$ speedup over the baseline implementation using C compiler. Furthermore, by parallelizing the single core implementation on the multi-core, we obtain $5.7{\times}{\sim}7.7{\times}$ speedup. The results we obtain show the possibility for applying the arithmetic-intensive deep neural network technology to applications on mobile devices.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.135-140
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• 2020

Recently, due to the rapid diffusion of intelligent systems and IoT technologies, power saving techniques in real-time embedded systems has become important. In this paper, we propose P-GA (Parallel Genetic Algorithm), a scheduling algorithm aims at reducing the power consumption of real-time systems in multi-core hybrid memory environments. P-GA improves the Proportional-Fairness (PF) algorithm devised for multi-core environments by combining the dynamic voltage/frequency scaling of the processor with the nonvolatile memory technologies. Specifically, P-GA applies genetic algorithms for optimizing the voltage and frequency modes of processors and the memory types, thereby minimizing the power consumptions of the task set. Simulation experiments show that the power consumption of P-GA is reduced by 2.85 times compared to the conventional schemes.