• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.387-393
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• 2008

In this paper, we present an SDR (Software Defined Radio) handset modem platform which supports communication systems such as HSDPA (High Speed Downlink Packet Access), and WiBro (Wireless Broadband Portable Internet). The proposed SDR platform employs DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), and microprocessors in such a way that the various communication functions like HSDPA and WiBro can be programmed and downloaded to the hardware platform. The proposed SDR platform can be used for functional verification of the physical layers of the mobile handset system in the mobile communication network. We first demonstrate the receiving structure of the physical layer of the HSDPA and WiBro system. Then, the hardware implementation of the proposed SDR platform is shown with functions and optimized signal flows required at each mode. Finally, the link performance of each mode operating on the proposed SDR platform is presented through the internal loopback tests with the test vectors. The experimental performance has been compared with the computer simulation results.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.5
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• pp.1-8
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• 2005

SPEC CPU2000 is an widely used benchmark program, both in industry and in academy, for measuring compute-intensive performance of computer systems with various architectures. However, there has been little effort to investigate its characteristics with respect to hardware components. This paper presents the performance scalability of SPEC CPU2000 benchmark over CPU clock speed. For an Intel x86-based system running at various clock speed, we measure the performance of SPEC CPU2000 benchmark, and analyze the characteristic of SPEC CPU2000 in a system aspect. In the experiment, we found that the overall performance of SPEC CPU2000 increases monotonically and linearly as the CPU clock speed increases and that the scale efficiencies of SPEC CPU2000 component benchmarks are quite evenly distributed.

• The Journal of the Acoustical Society of Korea
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• v.15 no.5
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• pp.73-81
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• 1996

In multiprocessor systems with multiple processors and memories, efficient communication between processors and memories is critical for high performance. Various types of multistage networks have been proposed. The economic feasibility and the improvements in both computing throughput and fault tolerance/diagnosis have been some of the most important factors in the development of these computer systems. In this paper, we present an efficient algorithm for the diagnosis of generalized cube interconnection networks with a fan-in/fan-out of 2. Also, using the assumed fault model present total fault diagnosis by generating suitable fault-detection and fault-location test sets for link stuck fault, switching element fault in direct/cross states, including broadcast diagnosis methods based on some basic properties or generalized cube interconnection networks. Finally, we illustrate some example.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.133-140
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• 2020

We discuss the method of a high precision range trigger and generation for a high range resolution radar. To verify the designed range resolution performance, we use test-equipments which can absolutely make a precision range shorter than the desined range resolution. The accuracy of generated range is proportional to the system reference clock. However, the system main processor is limited to input reference clocks and a higher available one is expensive in the conventional method. To solve this problem, we proposed that the range trigger and generation method using multi-phase-shiftings and integration. Through a experiment, we verified that the proposed method made problems which can be ocurred in the conventional method clear.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Geophysics and Geophysical Exploration
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• v.20 no.3
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• pp.129-136
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• 2017

3D seismic data processing methods such as full waveform inversion or reverse-time migration require 3D wave propagation modeling and heavy calculations. We compared efficiency and accuracy of a Xeon Phi coprocessor to those of a high-end server CPU using 3D frequency-domain wave propagation modeling. We adopted the OpenMP parallel programming to the time-domain finite difference algorithm by considering the characteristics of the Xeon Phi coprocessors. We applied the Fourier transform using a running-integration to obtain the frequency-domain wavefield. A numerical test on frequency-domain wavefield modeling was performed using the 3D SEG/EAGE salt velocity model. Consequently, we could obtain an accurate frequency-domain wavefield and attain a 1.44x speedup using the Xeon Phi coprocessor compared to the CPU.

• Journal of the Korean Data and Information Science Society
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• v.26 no.5
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• pp.1035-1045
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• 2015

Recent studies in Big Data Analysis are showing promising results, utilizing the main memory for rapid data processing. In-memory computing technology can be highly advantageous when used with high-performing servers having tens of gigabytes of RAM with multi-core processors. The constraint in network in these infrastructure can be lessen by combining in-memory technology with distributed parallel processing. This paper discusses the research in the aforementioned concept applying to a test taxi hailing application without disregard to its underlying RDBMS structure. The application of IMDG technology in the application's backend API without restructuring the database schema yields 6 to 9 times increase in performance in data processing and throughput. Specifically, the change in throughput is very small even with increase in data load processing.

• Journal of IKEEE
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• v.22 no.3
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• pp.619-623
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• 2018

Due to the development of society, the demand for electric power has increased and the quality control of electric power has become an important issue. In order to efficiently perform such power management, we propose a DSP based power measurement system for multi-wire power measurement. Since the conventional power measurement system can measure only the power of one line, a power quality measurement device is required for each line in order to measure the power quality of the individual line. Respectively. The system proposed in this paper proposes a system capable of real-time measurement of power quality at up to 12 points using digital signal processing algorithm, and the prototype based on this system was evaluated through the official test report of Korea Electrotechnology Research Institute. As a result of the performance test, it was evaluated that the error range is excellent at ${\pm}0.3%$.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.2
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• pp.202-208
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• 2001

A Switched Reluctance Motor(SRM) has double salient poles structure and the phase windings are wound in stator. SRM hase more simple structure that of other motor, thus manufacture cost is low, mechanically strong, reliable to a poor environment such as high temperature, and maintenance cost is low because of brushless. SRM needs position detector to get rotator position information for phase excitation and tachometer or encoder for constant speed operation. But, this paper doesn\`s use an encoder of high cost for velocity measurement of rotator. Instead of it, the algorithm for position detection and velocity estimation from simple slotted disk has been proposed and developed. To implement variable speed digital control system with velocity estimation algorithm, the TMS320F240-20MIPS fixed point arithmetic processor of TI corporation is used. The experimental results of the developing system are enable to control speed with wide range, not only single pulse, hard chopping mode and soft chopping, ut also variable speed control, and advance angle control.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3C
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• pp.359-367
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• 2004

The postprocessing to remove false minutia is important because the extraction of true minutia affects the performance as a key factor in fingerprint identification system. In this paper, we propose an efficient postprocessing algorithm for removing false minutia among the extracted candidates in a thinned image. The proposed algorithm removes false minutia in three steps by using various information in the acquired fingerprint image: the structural information of minutia (end point and bifurcation), the inherent characteristics of fingerprint, and the quality of acquired images. Under Intel Celeron processor environment with 248${\times}$292 images acquired by optic device, the experiments showed that the proposed algorithm efficiently removed false minutia while preserving true minutia. Moreover, the proposed algorithm takes 0.0154 second, which is very small compared to the time for preprocessing (0.343 second).