• Electronics and Telecommunications Trends
• /
• v.18 no.6 s.84
• /
• pp.19-26
• /
• 2003

다양한 이동통신기기들을 한 시스템에 수렴시킬 수 있는 기술로서 SDR 기술이 각광받고 있다. 본 논문은 W-CDMA 물리계층 업링크의 트래픽 채널을 DSP로 구현하여 베이스밴드 프로세싱 하는 것을 목적으로 한다. 이러한 소프트웨어 모뎀은 초기화, 소스 데이터 발생, 스프레딩, 스크램블링, 출력단 등으로 이루어진다. 기존의 FPGA, ASIC 등으로 구현된 하드웨어 모뎀을 소프트웨어적인 DSP로 구현할 때 생기는 주요 문제들을 고찰하였다. 로드 밸런싱, 동시성과 실시간성, 버퍼 스킴, 멀티 태스킹, 인터럽트 관리, OVSF 및 스크램블링 코드의 복소수 연산 등이다. 전통적인 구조는 FPGA와 DSP 혼합체인데 각각 칩레벨 프로세싱, 심볼 프로세싱을 담당한다. FPGA와 DSP 혼합체 구조를 넘어서 멀티 DSP를 이용한 병렬처리기법, 또는 reconfiguable 칩을 개발해서 칩레벨 및 심볼 프로세싱을 한 번에 할 수 있는 개발제품도 출시되었다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.6
• /
• pp.1194-1201
• /
• 2003

Measurements of network traffic have shown that self-similarity is a ubiquitous phenomenon spanning across diverse network environments. We have advance the framework of multiple time scale congestion control and show its effectiveness at enhancing performance for fast TCP prototype control. In this paper, we extend the fast TCP prototype control framework to window-based congestion control, in particular, TCP. This is performed by interfacing TCP with a large time scale control module which adjusts the aggressiveness of bandwidth consumption behavior exhibited by TCP as a function of "large time scale" network state. i.e., conformation that exceeds the horizon of the feedback loop as determined by RTT. Performance evaluation of fast TCP prototype is facilitated by a simulation bench-mark environment which is based on physical modeling of self-similar traffic. We explicate out methodology for discerning and evaluating the impact of changes in transport protocols in the protocol stack under self-similar traffic conditions. We discuss issues arising in comparative performance evaluation under heavy-tailed workload. workload.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.8
• /
• pp.1486-1491
• /
• 2017

In this paper, we propose a private multimedia caching scheme based on wireless local area network (WLAN) to improve the quality of service for high capacity and high quality multimedia streaming services which are recently increasing and to reduce the traffic load of core networks. The proposed caching scheme stores multimedia in the storage device mounted on WLAN APs and provides streaming services on its own without Internet connection in accordance with the request from clients. We have implemented a test network based on real commercial networks and measured the performance of the proposed caching scheme in terms of frames per second (FPS) and buffering time. According to the performance measurement results, the proposed caching scheme can reduce the average buffering time by 73.3% compared to the conventional streaming scheme. In addition, the proposed caching scheme can also improve the average FPS by 71.3% compared to the conventional streaming scheme.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.6
• /
• pp.145-155
• /
• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.11
• /
• pp.24-35
• /
• 2012

In this paper, we propose a dynamic lane control scheme with a traffic predictor module and a rate controller for reconciling with commercial optical PHY modules in energy efficient optical Ethernet systems. The commercial high speed optical Ethernet system capable of 40/100Gbps employs 4 or 10 multiple optical transceivers over WDM or multiple optical links. Each of the transceivers is always turned on even if the link is idle. To save energy, we propose the dynamic lane control scheme. It allows that several links may be entirely turned off in a low traffic load and frames are handled on the remaining active links. To preserve the byte order even if the number of active links may be changed, we propose a rate controller to be sat on the reconciliation sublayer. The main role of the controller is to insert null byte streams into the xGMII of inactive lanes. For the PHY module, the null input streams corresponding to inactive lanes will be disregarded on inactive PMDs. It is very handy to implement the rate controller module with MAC in FPGA without any modification of commercial PHYs. It is very crucial to determine the number of active links based on the fluctuated traffic load, we provide a simple traffic predictor based on both the current transmission buffer size and the past one with different weighting factors for adapting to the traffic load fluctuation. Using the OMNET++ simulation framework, we provide several performance results in terms of the energy consumption.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.5
• /
• pp.102-111
• /
• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• The Journal of the Acoustical Society of Korea
• /
• v.29 no.1
• /
• pp.48-55
• /
• 2010

It has a falling off in speech quality, especially when consecutive packet loss occurs, even if a vocoder implemented in the packet network has its own packet loss concealment (PLC) algorithm. PLC algorithm is divided into transmitter and receiver algorithm. Algorithm in the transmitter gives superior quality by additional information. however it is impossible to provide mutual compatibility and it occurs extra delay and transmission rate. The method applied in the receiver does not require additional delay. However, it sets limits to improve the speech quality. In this paper, we propose a new method that puts extra information for PLC in a part of Extension Header Data which is not used in RTP Header. It can solve the problem and obtain enhanced speech quality. There is no extra delay occurred by the proposed algorithm because there is a jitter buffer to adjust network delay in a receiver. Extra information, 16 bits each frame for G.729 PLC, is allocated for MA filter index in LP synthesis, excitation signal, excitation signal gain and residual gain reconstruction. It is because a transmitter sends speech data each 20 ms when it transfers RTP payload. As a result, the proposed method shows superior performance about 13.5%.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.5
• /
• pp.1397-1408
• /
• 1998

Service networks for the future communication networks will be combined by the B-ISDN networks. These service networks also will use SS No.7 as the signaling transport network for the control of user requriement service. Therefore, ITU-T recommended B-ISDN signaling layers for SS No.7 as a substitute for N-ISDN MTP signaling layer. In this paper, we propose the implementation structure and describe the characteristics and functions of each signaling layer of SS No.7, which are adapted to ATM switching system, and evaluate a performance. The structure of SSCOP transmission buffer using a linked list and an unit frame length is proposed for SAAL layer and the implementation structure and internal routing method according to the ATM switching system are also proposed for MTP-3b layer. Additionally, we propose the ISUP/B-ISUP level interworking structure using only associated mode, which are presented in the first stage of B-ISDN as the effective internatworking structure of SS No.7 for the circuit related signaling network between the existing N-ISDN networks and B-ISDN networks.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.1 no.2
• /
• pp.102-109
• /
• 2006

In this paper, we improve the performance of bidirectional TCP connection over end-to-end network that uses transfer rate-based flow and congestion control. The sharing of a common buffer by TCP packets and acknowledgement has been known to result in an effect called ack compression, where acks of a connection arrive at the source bunched together, resulting in unfairness and degraded throughput. The degradation in throughput due to bidirectional traffic can be significant. For example, even in the simple case of symmetrical connections with adequate window size, the connection efficiency is improved about 20% for three levels of background traffic 2.5Mbps, 5.0Mbps and 7.5Mbps. Otherwise, the throughput of jitter is reduced about 50% because round trip delay time is smaller between source node and destination node. Also, we show that throughput curve is improved with connection rate algorithm which is proposed for TCP congestion avoidance as a function of aggressiveness threshold for three levels of background traffic 2.5Mbps, 5Mbps and 7.5Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1C
• /
• pp.1-8
• /
• 2004

This paper proposes a novel algorithm for a low power turbo decoder based on reduction of number of decoding iterations, targeting power-critical mobile communication devices. Previous researches that attempt to reduce number of decoding iterations, such as CRC-aided and LLR methods, either show degraded BER performance in return for reduced complexity or require additional hardware resources for controlling the number of iterations to meet BER performance, respectively. The proposed algorithm can reduce power consumption without degrading the BER performance, and it is achieved with minimal hardware overhead. The proposed algorithm achieves this by comparing consecutive hard decision results using a simple buffer and counter. Simulation results show that the number of decoding iterations can be reduced to about 60% without degrading the BER performance in the proposed decoder, and power consumption can be saved in proportion to the number of decoding iterations.