• Proceedings of the Korea Information Processing Society Conference
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• 2003.11a
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• pp.339-342
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• 2003

배치는 칩의 성능 및 레이아웃에 결정적인 영향을 주는 요인으로써 크게 광역배치와 상세배치 두단계를 거쳐 이루어지며 수년 동안 다양한 기법들이 개발되어 왔다. 본 논문에서는 표준 셀 배치를 개선하기 위한 동적 프로그래밍 기법을 이용한 최적 인터리빙 알고리즘을 확장하여 선을 동일 행 내에서만 움직이던 한계점을 극복하여 서로 다른 행 사이에서도 움직일 수 있도록 하였다. 즉, 셀들은 주어진 배치 내에서 임의의 위치로 움직일 수 있어 배치가 더욱 효율적으로 최적화 될 수 있도록 하였다.

• 전자공학회논문지 IE
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• v.48 no.2
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• pp.6-11
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• 2011

This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor's parameters. Physical implementation of phase error accumulation method(PHEAM) can be easy integrated at the same chip as close as possible to the device under test(DUT). It was implemented as digital IP core for semiconductor manufacturing process($0.11{\mu}m$, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1110-1116
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• 2013

A 3D-ray tracing tool is a software considering reflection, penetration, and diffraction of the signals to provide accuracy. To provide communication resources effectively, communication standards adopt Heterogeneous Networks (HetNets) that includes small cells. A 3D performance evaluation methodology becomes more and more important since the coverage of the small cell networks is narrower than that of the macro cell networks. It is difficult to directly apply conventional 2D mathematical models due to the complexity of small cell network; since they have many considerations such as topography, placement of buildings and 3D beamforming techniques. In this paper, we introduce an effective performance evaluation methodology for small cell networks using 3D-ray tracing tool. From simulation results, we conclude that new performance evaluation methodologies by using 3D-ray tracing tool is more suitable than conventional methodology for small cell networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1B
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• pp.31-38
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• 2012

In this paper, we propose a method to improve cell edge users' performance in HetNet (heterogeneous network) systems by cooperatively transmitting signals using remote radio heads (RRHs) located near coverage boundaries, referred to as edge RRHs. The proposed method locates the edge RRHs in specific locations of the cell boundary and provides an efficient operational strategy by adjusting the duty cycle of the edge RRHs and base stations. The effectiveness of the method is demonstrated by experimental performance based on the system model parameters of the CoMP (coordinated multi-point transmission and reception) scenario, which is discussed in LTE-Advanced (Long Term Evolution - Advanced) standard contributions. When compared with conventional methods, utilization of edge RRHs is especially advantageous for the performance improvement of lower percentile users in terms of average throughput and effectively improves the fairness among users.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1598-1605
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• 1989

This paper describes an efficient global cell (module) placement strategy called HALO (Hierarchical Alternating Linear Ordering)which generates global 2-D placement of circuit modules by hierarchical application of linear ordering in alternating direction. We tried, in principle, to explain why HALO should perform better than other typical, somehat successful, analytical approaches such as min-cut, force-directed relaxation(FDR)or its likes. We have implemented HALO as a program for standard cell placement. Experimental results on two benchmark circuits, primary and primary 2 consisting of 752 and 2907 cells, respectively have shown a decrease of half-perimeter routing length by 7% and 24%, respectively compared to the best available results obtained so far. Total CPU time including the following detailed placement was less than half of the earlier work.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1074-1079
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• 1987

We present a fast, constructive algorithm for the automatic placement of standard cells, which consists of two steps. The first step is responsible for cell-row assignment of each cell, and converts the circuit connectivity into a multi-stage graph under to constraint that sum of the cell-widths in each stage of the multi-state graph does not exceed maximum cell-row width. Generatin of feed-through cells in the final layout was shown to be drastically reduced by this step. In the second step, the position of each cell within the row is determined one by one from left to right so that the cost function such as the local channel density is minimized. Our experimental result shows that this algorithm yields near optimal results in terms of the number of feed-through cells and the horizontal tracks, while running about 100 times faster than other iterative procedures such as pairwise interchange and generalized force directed relaxation method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.15-25
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• 2012

The research on the FPGA CAD tools in academia has been lacking practicality due to the underlying FPGA fabric architecture which is too simple and inefficient to be applied for commercial FPGAs. Recently, the database of placement positions and routing graphs on commercial FPGA architectures has been built, and provided for enabling the academic development of placement and routing tools. To extend the limit of academic CAD tools even further, we have developed the evaluation toolkit for the K-FPGA architecture which is under development. By providing interface for exchanging data with a commercial FPGA toolkit at every step of mapping, packing, placement and routing in the tool chain, the toolkit enables individual tools to be developed without waiting for the results of the preceding step, and with no dependency on the quality of the results, and compared in detail with commercial tools at any step. Also, the fabric primitive library is developed by extracting the prototype from a reporting file of a commercial FPGA, restructuring it, and modeling the behavior of basic gates. This library can be used as the benchmarking target, and a reference design for new FPGA architectures. Since the architecture is described in a standard HDL which is familiar with hardware designers, and read in the tools rather than hard coded, the tools are "data-driven", and tolerable with the architectural changes due to the design space exploration. The experiments confirm that the developed library is correct, and the functional correctness of applications implemented on the FPGA fabric can be validated by simulation. The placement and routing tools are under development. The completion of the toolkit will enable the development of practical FPGA architectures which, in return, will synergically animate the research on optimization CAD tools.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.7
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• pp.490-499
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• 2017

In recent years, the introduction of complex systems analysis based on various variables has become more active in order to identify and analyze complex problems of Modern Society. Prediction of patients' spatial perception and usability according to the spatial arrangement of the outpatient department is a very important factor for providing high quality hospital service. For objective analysis, the standard program procedure and analysis index for the diseases of the elderly were prepared and the uniformity of the atmospheric space was evaluated through heat map analysis and quantitative analysis. In this study, 73 cells were installed and simulated to analyze the uniformity of the four alternatives according to the change of the arrangement of the medical care space, receiving space, and consultation space using the complex system analysis method for the nursing hospitals. The resulting density was derived. The results are as follows. 1)The layout of the reception space has the greatest influence on the total spatial density of the waiting space. 2) The uniformity of the waiting space can be increased by separating the examination space and the examination space. 3)The closer the location of the receiving space is from the entrance, the greater the density of the waiting space. Finally, this study applied discrete event simulation to the evaluation of uniformity of atmosphere space, and proved that the actor - based model can be utilized for utilization and evaluation as spatial analysis methodology.

• The Journal of the Acoustical Society of Korea
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• v.14 no.5
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• pp.63-73
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• 1995

The conventional acoustic sounds can be synthesized by Frequency Modulation which includes the variation of frequency, amplitude, and modulation index. In this paper the number of variable synthesis parameters are limited to easily implement the existing two carrier FM algorithm by hardware. The DSP(Digital Signal Processor), which is able to carry out the modified algorithm and synthesize 16 sounds at a time, is designed with $0.8{\mu}m$ standard sells. The DSP which can synthesize 2 sounds at a time is implemented by ASIC emulator to examine the sound quality of the designed DSP. Through the objective and subjective estimation, it is confirmed that the sounds of many instruments from the implemented DSP are very closed to their real sound. Finally the designed DSP is layouted and simulated by VLSI desgn tool. According to the simulation, the designed DSP has the sufficiently fast speed for synthesizing 16 sounds at a time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.