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Lee, Ji-Hwan;Park, Hee-Gon;Park, Gi-Hong
- Proceedings of the Korean Institute of Building Construction Conference
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- 2016.05a
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- pp.175-176
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- 2016
In this study, research is in order to prevent the defects that occur when the polished tiles construction. For material to be used when the polishing tile construction, trying to evaluate the shrinkage characteristics when the environmental conditions change. Depending on the material used for the shrinkage characteristics evaluation results, the difference between the change values of the length of the drying shrinkage becomes large. Therefore, there is a need for the construction method with consideration of the characteristics of the materials used.
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김성구;윤형도;윤대원;한상필;박계춘;유용택
- Electrical & Electronic Materials
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- v.10 no.7
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- pp.682-691
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- 1997
We have investigated the guided optical properties of a Ti:LiNbO$_3$optical waveguide which was fabricated by Ti-diffusion in an air atmosphere and proposed an effective polishing method of waveguide endfaces. And the results of guided optical mode and fabrication condition were obtained as follows; \circled1 propagation loss : 0.53 dB/cm \circled2 mode size : horizontal/vertical=12.5${\mu}{\textrm}{m}$ \circled3 mode mismatch : 1.7 dB \circled4 diffusion temperature : 105$0^{\circ}C$, time : 8 hours \circled5 atmosphere : air
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Jeong, Hea-do
- Journal of the Korean Society for Precision Engineering
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- v.13 no.11
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- pp.46-56
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- 1996
Planarization technique is rapidly recognized as a critical step in chip fabrication due to the increase in wiring density and the trend towards a three dimensional structure. Global planarity requires the preferential removal of the projecting features. Also, the several materials i.e. Si semiconductor, oxide dielectric and sluminum interconnect on the chip, should be removed simultaneously in order to produce a planar surface. This research has investihgated the development of the chemical mechanical polishing(CMP) machine with uniform pressure and velocity mechanism, and the pad insensitive to pattern topography named hard grooved(HG) pad for global planarization. Finally, a successful result of uniformity less than 5% standard deviation in residual oxide film and planarity less than 15nm in residual step height of 4 inch device wafer, is achieved.
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Song Eun-Jee
- Journal of Digital Contents Society
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- v.5 no.4
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- pp.251-256
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- 2004
The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.
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