• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.25-27
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• 2001

본 논문에서는 AE32000 프로세서에 적응 가능한 효율적인 분기 예측 기법에 관하여 연구하였다. 실험결과, 내장형 응용분야에서의 비용 효율성이란 측면에, AE32000 프로세서에서는 1비트의 분기 예측기와 한 개의 엔트리를 갖는 BTB(Branch Target Buffer)를 사용하는 것이 가장 적합함을 관찰하였다. 또한, 분기 목적 주소에서 나타나는 LERI 명령을 폴딩하여 분기 손실을 줄이는 방안은, BTB와 LERI 폴딩 유닛을 사용하는 설계에서, 가져오는 성능 향상이 미미함을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.35-42
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• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.767-775
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• 2001

본 논문에서는 비터비 검출기의 복잡도와 전력소모를 감소시킬 수 있는 폴딩 비터비 검출기를 제안하였다. 제안된 폴딩 비터비 검출기는 상태 천이도가 대칭적인 것을 이용하여 상태는 서로 반전된 값을 갖는 것끼리 묶어지며, 확률거리의 경우 서로 부호가 반대인 값끼리 묶여진다. 제안된 폴딩 비터비 검출기를 EPRML 읽기 채널에 적용할 경우 확률거리 계산에 필요한 두 개의 가산기를 하나의 가감산기로 대체하여 기존의 GVA 알고리즘에 비해 하드웨어 복잡도를 37.4% 감소시킬 수 있었다. 또한 불필요한 전력소모의 원인이 되는 글리치 발생을 신호 재배치와 병렬 구조와 같은 상위 수준의 저전력 기법을 적용하여 억제한 결과 12.7%의 전력소모 감소를 나타내었다.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.266-272
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• 2000

The square-based multiplication using look-up table simplifies the process and speeds-up the operating speed. However, the look-up table size increases exponentially as bit size increases. Recently, Wey and Shieh introduced a noble design of square generator circuit using a folding approach for high-speed performance applications. The design uses the ones complement values of ROM addresses to fold the huge look-up ROM table repeatedly such that a much smaller table can be sufficient to store the squares. We present new folding techniques that do not require a ones complement part, one of three major parts in the Wey and Shiehs method. Also the proposed techniques reduce the bit size of partial sums such that the hardware implementation be simplified and the performance be enhanced.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.61-69
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• 2010

In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.

• Journal of Korea Multimedia Society
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• v.12 no.9
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• pp.1288-1296
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• 2009

This paper is for multi-frequency thin film loop antenna used on smart phone, PMP and PDA like as a multi-media devices. We developed a loop pattern folding methods to reduce a thin film antenna dimension using that mutual coupling folding loop occurs the higher frequency resonation. To reduce the thin film size for loop antenna, we fold the loop pattern repeatedly control the coupling coefficient than generate a not only higher mode resonation but also basic resonation from loop pattern. To realization the thin film folded loop antenna, we used a $30mm{\times}9mm$ PI film the thickness is 20um so that we realize the CDMA850, GPS, DCS, PCS, WCDMA antenna simultaneously and it's radiation efficiency is over 50% and gain is 0dBi.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.14-21
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• 2011

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.66-71
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• 2000

A new Soft Recovery Quasi-Resonant Converter (SR QRC) haying multiple order folding snubber network is proposed. It is combined with normal quasi-resonant converter with folding snubber network of which the surrounding components are composed of diodes and capacitors. The reverse recovery loss of main rectifier diode is eliminated by this method utilizing multiple resonance. The proposed converter has PWM capability with high efficiency and is suitable for high voltage and high power applications. By extension of this concept to other switching converters, a new family of SR PW QRC may be developed.