• Korean Journal of Optics and Photonics
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• v.5 no.1
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• pp.84-89
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• 1994

A tunable pulsed dye laser was operated in a single longitudinal mode by injection locking with a cw ring dye laser. A doubled Nd:YAG laser was used as the pumping source. Phase sensitive detection technique was applied to maintain the required match between the master laser frequency and the slave resonator cavity length. The fluctuation of the center frequency of the pulsed laser was < 10 MHz, and the pulse duration (FWHM) was 6 ns. The linewidth measured by scanning confocal interferometer was 130 MHz. When pumped by 50 mJ of the doubled Nd:YAG laser, the output energy of the pulsed dye laser was 2 mJ and the peak power was 330 kW. 30 kW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.14-21
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• 1992

An optical novelty filter is implemented using photorefractive materal(BaTiO$_{3}$) as a recording materal and commercial liquid crystal TV as a spatial light polarization modulator. If a signal beam incident at the proper, the loop and the crossing angle inside th e crystal is formed to get maximum diffraction efficiency and BaTiO$_{3}$ as a self-pumped phase conjugation mirror show that phase conjugate reflectivity was 20 times as much as ordinary polarization if signal beam is extraordinary. In this paper, the stoke's theorem which is a reciprocal theorem for which is a reciprocal theorem for beam path is experimentally proved, and good output images were obtained with optical experiment of novelty filter which is formed by use of Michelson interferometer.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.43-51
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• 1993

Effects of incident beam position and intensity on self-pumped optical phase conjugation are presented using barium titanate as an optical phase conjugator. Depending on the position of incident beam, the crystal used consists of four major operating regions: irregular pulsing, regular pulsing, stable phase conjugation, and unstable oscillating regions. In the second region, the pulsing frequency and amplitude of phase conjugate beam are proportional to I$_{in}$ and I$_{in}^{0.85}$, respectively, where I$_{in}$ is the incident beam intensity. In the fouth region, the rising time and intensity of the first-generated pulse are proportional to I$_{in}^{0.92}$ and I$_{in}^{0.81}$, respectively. A frequency shift by beam fanning is also discussed by observing interference pattern from an interferometer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Korean Journal of Optics and Photonics
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• v.12 no.5
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• pp.371-375
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• 2001

We have implemented a sensor head which consists of erbium doped fiber pumped by 1480 nm LD and single fiber Bragg grating for simultaneous measurement of strain and temperature. The measurement precision and speed are improved by using Mach-Zehnder interferometer instead of optical spectrum analyzer (OSA) as a demodulator. The measurement precision of temperature measured by the amplitude variation of output signal is 0.05$^{\circ}C$ and that of strain measured by the phase variation of output signal is 0.1$\mu$strain. The measurement precision of temperature and strain are improved nearly 140 times and 700 times, respectively, compared to those using an OSA with wavelength resolution of 0.97 nm as d demodulator.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.