• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.7
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• pp.515-520
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• 2014

In this paper, the protograph-based block low density parity check (LDPC) code, which improves the performance and reduces the encoder/decoder complexity than the conventional Digital Video Broadcasting Satellite Second Generation (DVB-S2) LDPC code used for the marine satellite communication, is proposed. The computer simulation results verify that the proposed protograph-based LDPC code has the better performance in both the bit error rate (BER) and the frame error rate (FER) than the conventional DVB-S2 LDPC code. Furthermore, by analyzing the encoding and decoding computational complexity, we show that the protograph-based block LDPC code has the efficient encoder/decoder structure.

• Journal of KIISE:Information Networking
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• v.36 no.5
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• pp.389-396
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• 2009

In RFID systems, identifying the tag attached to the subject begins with the request from a reader. When the reader sends a request, multiple tags in the reader's interrogation zone simultaneously respond to it, resulting in collision. The reader needs the anti collision algorithm which can quickly identify all the tags in the interrogation zone. We propose the Anti Collision Algorithm using Parity Mechanism(ACPM). In ACPM, a collision can be prevented because the tags which match with the prefix of the reader's request respond as followings; the group of tags with an even number of 1's in the bits to the prefix + 2nd bits responds in slot '0', while the group of tags with an odd number of 1's responds in slot '1'. The ACPM generates the request prefix so that the only existing tags according to the response in the corresponding slot. If there are two collided bits in tags, then reader identify tags by the parity mechanism. That is, it decreases the tag identification time by reducing the overall number of requests.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.287-290
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• 2011

분산 동영상 부호화 시스템에서는 복호기에서 움직임 보상 보간 기법을 이용하여 부가정보를 생성한다. 생성된 부가정보와 원 Wyner-Ziv 프레임간의 차이를 채널 부호로 오류 정정하게 되는데 이때 부호기에서는 복호기에서의 오류 정정을 위하여 패리티 비트인 Wyner-Ziv 비트를 복호기로 보내게 되고 복호기에서는 이 Wyner-Ziv 비트를 이용하여 Wyner-Ziv 프레임을 복원하는데 더 많은 Wyner-Ziv 비트가 필요할 경우 피드백 채널을 통해 Wyner-Ziv 비트를 요청하게 된다. 이때 부호기에서 조건부 엔트로피를 구할 수 있다면 이를 이용하여 Wyner-Ziv 비트 전송량을 제어함으로써 피드백 채널을 제거 할 수 있다. 이를 위해 부호기에서도 부가정보를 알아야하는데 복호기에서 사용하는 부가정보 생성 기법은 복잡도가 높기 때문에 사용할 수 없다. 본 논문에서는 부호기에서 간단한 부가정보를 생성하는 방법을 제안하고 분산 동영상 부호화 시스템에 적용하여 피드백 채널을 제거하였을 때의 성능을 분석하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1675-1685
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• 2012

DVC (Distributed Video Coding) technique plays an essential role in providing low-complexity video encoder. But, in order to achieve the better rate-distortion performances, most DVC systems need feedback channel for parity bit control. This causes the DVC-based system to have high decoding latency and becomes as one of the most critical problems to overcome for a real implementation. In order to overcome this problem and to accelerate the commercialization of the DVC applications, this paper analyzes an effect of LDPCA frame size for adaptive LDPCA frame-based parity bit request estimations. First, this paper presents the LDPCA segmentation method in pixel-domain and explains the temporal-based bit request estimation method and the spatial-based bit request estimation method using the statistical characteristics between adjacent LDPCA frames. Through computer simulations, it is shown that the better performance and fast decoding is observed specially when the LDPCA frame size is 3168 in QCIF resolution.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.948-953
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• 2010

In this paper, we propose multi-bit soft error detection method which can use an instruction cache of superscalar CPU architecture. Proposed method is applied to high-speed static RAM for instruction cache. Using 1D parity and interleaving, it has less memory overhead and detects more multi-bit errors comparing with other methods. It only detects occurrence of soft errors in static RAM. Error correction is treated like a cache miss situation. When soft errors are occurred, it is detected by 1D parity. Instruction cache just fetch the words from lower-level memory to correct errors. This method can detect multi-bit errors in maximum 4$\times$4 window.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.423-431
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• 2010

In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.137-146
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• 1997

The simplest bit error detection scheme is to append a parity bit to the end of a bit sequence. In this paper an error correction technique with the use of a parity bit is proposed, and the performance of the proposed system is analyzed. The error probability of the proposed system is compared with the output of computer simulation of the proposed system. It is also compared with the error probability of error at BPSK system, and the signal-to-noise ratio gain is showed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.14-19
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• 2006

The high encoding complexity of LDPC codes can be solved by designing structured parity-check matrix. If the parity-check matrix of LDPC codes is composed of same type of blocks, decoder implementation can be simple, this structure allow structured decoding and required memory for storing the parity-check matrix can be reduced largely. In this parer, we propose a construction algorithm for short block length structured LDPC codes based on girth condition, PEG algorithm and variable node connectivity. The code designed by this algorithm shows similar performance to other codes without structured constraint in low SNR and better performance in high SNR than those by simulation

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.59-64
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• 2004

We propose a new RLL(run length limited) (2,7) PP(parity preserving) code with 4 RMTR(repeated minimum transition run) for optical recording. The proposed code has better characteristics in terms of density ratio, RMTR, DC(direct current) component suppression, BER(bit error rate) and system complexity than (2,1O) code that currently applied in storage systems and (1,7) PP code that highly recommended as the next generation optical recording system. Some characteristics of the code are described with several simulations. And the proposed code's superiorites in performance is illustrated as compared with the other codes.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.2 s.314
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• pp.11-18
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• 2007

Back propagation algorithm based on a gradient-decent method has been widely used to the training of a neural network. However, this algorithm have some problems such as dropping the minimum value in a local area according to an initial value and setting the number of units in a hidden layer when training the neural network. Accordingly, to solve the above-mentioned problems, this paper proposes a genetic algorithm using the training method of the neural network. Thus, the improved genetic algorithm using a new crossover and mutation method is proposed to discriminate 3 bit parity. Experiments confirm that the proposed system is effective for training speed after demonstrating for generation gap, the number of units in the hidden layer, and the number of individuals.