• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1633-1640
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• 2013

In this paper, noise parameters for high frequency modeling of dual-gate FET are extracted and analyzed. To extract thermal noise parameter of dual gate, noise characteristics are measured by changing input impedance of noise source using Tuner, and the influence of pad parasitic elements are subtracted using open and short dummy structure. Measured results indicated that the dual-gate FET is improved the noise figure by 0.2dB compared with conventional cascode structure FET at 5GHz, and it confirmed that the noise figure has dropped due to reduction of capacitances between the drain and source, gate and drain by simulation and analysis of small-signal parameters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.651-652
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• 2005

Chemical mechanical polishing (CMP) has emerged as the planarization technique of choice in integrated circuit manufacturing. Especially, polishing pad is considered as one of the most important consumables because of its properties. Generally, conventional polishing pad has irregular pores and asperities. If conditioning process is except from whole polishing process, smoothing of asperities and pore glazing occur on the surface of the pad, so repeatability of polishing performances cannot be expected. In this paper, CMP pad with microstructure was made using micro-molding technology and repeatability of ILD(interlayer dielectric) CMP performances and was evaluated.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.26-34
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• 1998

This paper presents a characterization method for faults of circuit patterns on MCM(Multichip Module) or PCB(Printed Circuit Board) substrates with electron beams of a SEM(Scanning Electron Microscope) by inducing voltage contrast on the signal line. The experimentation employes dual potential electron beams for the fault characterization of circuit patterns with a commercial SEM without modifying its structure. The testing procedure utilizes only one electron gun for the generation of dual potential electron beams by two different accelerating voltages, one for charging electron beam which introduces the yield of secondary electron $\delta$ < 1 and the other for reading beam which introduces $\delta$ > 1. Reading beam can read open's/short's of a specific net among many test nets, simultaneously discharging during the reading process for the next step, by removing its voltage contrast. The experimental results of testing the copper signal lines on glass-epoxy substrates showed that the state of open's/short's had generated the brightness contrast due to the voltage contrast on the surface of copper conductor line, when the net had charged with charging electron beams of 7KV accelerating voltages and then read with scanning reading electron beams of 2KV accelerating voltages in 10 seconds. The experimental results with Au pads of a IC die and Au plated Cu pads of BGA substrates provided the simple test method of circuit lines with 7KV charging electron beam and 2KV reading beam. Thus the characterization method showed that we can test open and short circuits of the net nondestructively by using dual potential electron beams with one SEM gun.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.362-370
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• 2010

In this paper, a compact RF Front-end module for Wireless Fidelity(Wi-Fi) and Worldwide Interoperability for Microwave Access(WiMAX) applications is realized by low temperature co-fired ceramic(LTCC) technology. The RF Front-end module is composed of three LTCC band-pass filters, a Film Bulk Acoustic Resonator(FBAR) filter, fully embedded matching circuits, an SPDT switch for mode selection, an SPDT switch for Tx/Rx selection, and an SP4T switch for band selection. The parasitic elements of 0.2~0.3 pF are generated by the structure of stacking in the top pad pattern for DC block capacitor of SPDT switch for mode selection. These kinds of parasitic elements break the matching characteristic, and thus, the overall electrical performance of the module is degraded. In order to compensate it, we insert a parallel lumped-element inductor on capacitor pad pattern for DC block, so that we obtain the optimized performance of the RF Front-end module. The fabricated RF front-end module has 12 layers including three inner grounds and it occupies less than $6.0mm{\times}6.0mm{\times}0.728mm$.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.1-9
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• 2002

The metallurgical reaction properties between the pad consisted of 0.5 $\mu\textrm{m}$Au/5 $\mu\textrm{m}$Ni/Cu layers on a conventional ball grid array (BGA) substrate and In-15 (wt.%)Pb-5Ag solder ball were characterized during the reflow process and solid aging. During the reflow process of 1 to 5 minutes, it was observed that thin $AuIn_2$ or Ni-In intermetallic layer was formed at the interface of solder/pad. The dissolution rate of the Au layer into the molten solder was about $2\times 10^{-3}$ $\mu\textrm{m}$/sec which is remarkably low in comparison with a eutectic Sn-37Pb solder. After solid aging treatment for 500 hrs at $130^{\circ}C$, the thickness of $Ni_{28}In_{72}$ intermetallic layer was increased to about 3 $\mu\textrm{m}$ in all the conditions nevertheless the initial reflow time was different. These result show that In atoms in the solder alloy were diffused through the $AuIn_2$ phase to react with underlaying Ni layer during solid aging treatment. From the microstructural observation and shear tests, the reaction properties between In-15Pb-5Ag alloy and Au/Ni surface finish were analyzed not to trigger Au-embrittlement in the solder joints unlike Sn-37Pb composition.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.3
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• pp.1428-1438
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• 2013

Services take place in Internet environment, a formation of the trust relationship between user and service provider for services. Different authentication schemes such as using Certificate of Public Key Infrastructure authentication and using ID/PW for a simple user authentication have been proposed for trust relationship. In addition, in the case of electronic financial transactions, transaction integrity and non-repudiation features are provided. These services are provided in Internet environment, use various measures to ensure service safety. However, it was difficult to prevent attacks using existing security technology because of emergence of MITB attack that manipulate the memory area of the Web browser and social engineering attacks such as phishing/pharming, requires application of new security technologies became. In this paper, we propose a concept of smart secure-pad, and utilize it safely formed a trust relationship between user and service provider, a model has been proposed to ensure safety of data transmission. Proposed model's security evaluation results show security against to MITB attack and phishing/pharming that can't be prevent attack using existing security technology. In addition, service provider can easily apply the model in safe environment can provide Internet service using provided representative services applying the proposed model.

• Polymer(Korea)
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• v.34 no.3
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• pp.226-236
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• 2010

UV irradiated acrylic pressure sensitive adhesives(PSAs) are prepared to be used for thermal pad in plasma display panel(PDP). The effect of the chemical structure of side-chain in comonomer and of crosslinking agent on wet-out property of acrylic PSAs in wide temperature range were investigated. The correlationship between viscoelastic behavior and adhesion properties, such as tack and peel strength, was also studied. The experimental results supported that wet-out and adhesion properties of acrylic PSAs were enhanced inversely proportional to side-chain length of comonomer in wide temperature range. The peel energy clearly increased in acrylic PSAs prepared by using di(ethylene glycol) dimethylacrylate (DEGDMA) for crosslinking agent. The results might be due to the difference in the glass transition temperature and viscoelastic behavior of acrylic PSAs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.57-66
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• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• Journal of the Korean Society for Nondestructive Testing
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• v.34 no.1
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• pp.38-43
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• 2014

An experimental method based on flexural wave propagation is proposed for identification of structural damage in rail fastening systems. The vibration of a rail clamped and supported by viscoelastic pads is significantly influenced by dynamic support properties. Formation of a defect in the rail fastening system induces changes in the flexural wave propagation characteristics owning to the discontinuity in the structural properties. In this study, frequency-dependent support stiffness was measured to monitor this change by a transfer function method. The sensitivity of wave propagation on the defect was measured from the potential energy stored in a continuously supported rail. Further, the damage index was defined as a correlation coefficient between the change in the support stiffness and the sensitivity. The defect location was identified from the calculated damage index.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.47-53
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• 2019

Stiffness-gradient stretchable electronic packages of the soft PDMS/hard PDMS/PTFE structure were processed using the polydimethylsiloxane (PDMS) as the base substrate and the more stiff polytetrafluoroethylene (PTFE) as the island substrate, and their stretchable deformation-resistance characteristics were characterized. The flip-chip joints, formed by bonding the chip bumps of 50 ㎛-diameter onto the PDMS/PTFE substrate pads, exhibited an average contact resistance of 96 mΩ. When the stretchable package of the soft PDMS/hard PDMS/PTFE structure was deformed to 30% elongation, the strain on the PTFE was restrained to 1%, resulting in a negligible resistance increase of 1% in the daisy-chain circuit formed on the PTFE island substrate. The circuit resistance increased for 1.7% after 2,500 cycles of 0~30% stretchable deformation.