• Journal of the Korean Geophysical Society
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• v.2 no.1
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• pp.39-44
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• 1999

High-resolution images are drawn from existing seismic data which were originally obtained by Korea Ocean Research & Development Institute (KORDI) during 1994-1997 for deep seismic studies on the East Sea of Korea. These images are analyzed for mapping Quaternary faults and near-bottom gas pockets. First 12 channels are selected from shot gathers for reprocessing. The processing sequence adopted for high-resolution seismic images comprises data copy, trace editing, true amplitude recovery, common-midpoint sorting, initial muting, prestack deconvolution, bandpass filtering, stacking, highpass filtering, poststack deconvolution, f-x migration, and automatic gain control (AGC). Among these processing steps, predictive deconvolution, highpass filtering, and short window AGC are the most significant in enhancement of resolution. More than 200 Quaternanry faults are interpreted on the migrated sections in the shallow depths beneath the seafloor. Although numerous faults are found mostly at the western continental slope and boundaries of the Ulleung Basin, significant amount of the faults are also indicated within the basin. Many of these faults are believed to be formed with reactivation of basement, from geotectonic activities including volcanism, and often originated in Tertiary, indicating that the tectonic regime of the East Sea might be unstable. Existence of shallow gas pockets casts real hazardous warnings to deep-sea drillings and/or to underwater constructions such as inter-island cables and gas pipelines. On the other hand, discovery of these gas pockets heightens the interests in developing natural resources in the East Sea. Reprocessed seismic sections, however, show no typical seismic characteristics for gas hydrates such as bottom-simulating reflectors in the western continental slope and ocean floor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.73-83
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• 2007

In network intrusion prevention, attack packets are detected and filtered out based on their attack signatures. Pattern matching is extensively used to find attack signatures and the most time-consuming execution part of Network Intrusion Prevention Systems(NIPS). Pattern matching is usually accelerated by hardware and should be performed at wire speed in NIPS. However, that alone is not good enough. First, pattern matching hardware should be able to generate sufficient pattern match information including the pattern index number and the location of the match found at wire speed. Second, it should support pattern grouping to reduce unnecessary pattern matches. Third, it should always have a constant worst-case performance even if the number of patterns is increased. Finally it should be able to update patterns in a few minutes or seconds without stopping its operations, We propose a system architecture to meet the above requirement. The system architecture can process multiple pattern characters in parallel and employs a pipeline architecture to achieve high speed. Using Xilinx FPGA simulation, we show that the new system stales well to achieve a high speed oner 10Gbps and satisfies all of the above requirements.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.271-274
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• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.