• The KIPS Transactions:PartD
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• v.10D no.2
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• pp.175-186
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• 2003

Mobile clients like a PDA need a cache and a spatial index to search and access map data efficiently. When a server transmits spatial objects to a mobile client which has a low storage capacity, some of them can be duplicated in a cache of the mobile client. Moreover, the cost for strong added data in the cache and reconfiguring spatial index is very high in the mobile client with low computing power. The scheme for processing duplicated objects and disturbing tasks of the mobile client which has low computing power is needed. In this paper, we classfy the method for strorng duplicated objects and present the scheme for the both caching objects and reconfiguring a spatial index of cached objects using the clipping technique. We propose the caching system based on an agent in order to distribute the overhead of a mobile client as well as to provide efficiently map services. We design and implement it, and evaluate the performance.

• Journal of Industrial Convergence
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• v.21 no.2
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• pp.103-109
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• 2023

In Korea, software education is implemented from elementary school. As a representative software education tool for elementary schools, various chess games reconstructed based on the rules of Western chess games are being used. On the other hand, Yutnori, one of our traditional games, also includes elements of software education, so research on this is needed. Therefore, in this study, a Yutnori program based on computational thinking using an educational programming language, Entry, and a turtle robot was developed and its validity verified. As a result of the validity verification, the CVR value was higher than 0.7 in the degree of agreement with the subject achievement standard (3 questions), the appropriateness of learning materials (4 questions), and the possibility of class application (3 questions). Therefore, it could be judged that the learning program developed in this study has a high level of agreement with the subject achievement standards, appropriate learning materials, and high possibility of being applied to classes. In order to generalize this content in the future, the effectiveness will need to be verified, and experimental research will be needed to understand this.

• Journal of the Korean Society of Radiology
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• v.2 no.2
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• pp.31-38
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• 2008

Line scan diffusion weighted imaging (LSDI) pulse sequence for 0.32 T magnetic resonance imaging (MRI) system was developed. In the LSDI pulse sequence, the imaging volume is formed by the intersection of the two perpendicular planes selected by the two slice-selective $\pi$/2-pulse and $\pi$-pulse and two diffusion sensitizing gradients placed on the both side of the refocusing $\pi$-pulse and the standard frequency encoding readout was followed. Since the maximum gradient amplitude for the MR system was 15 mT/m the maximum b value was $301.50s/mm^2$. Using the developed LSDI pulse sequence, the diffusion weighted images for the aqueous NaCl solution phantom and triacylglycerol solution phantom calculated from the line scan diffusion weighted images gives the same results within the standard error range (mean diffusivities = $963.90{\pm}79.83({\times}10^{-6}mm^2/s)$ at 0.32 T, $956.77{\pm}4.12({\times}10^{-6}mm^2/s)$ at 1.5 T) and the LSDI images were insensitive to the magnetic susceptibility difference and chemical shift.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.80-89
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.224-234
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.79-85
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• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.