• Title/Summary/Keyword: 통신단락

Search Result 129, Processing Time 0.025 seconds

Equivalent Admittance and Complex Powers in a Coupling through a Narrow Slit in a Parallel-Plate Waveguide (평행평판도파관의 좁은 슬릿을 통한 결합에 있어서 등가어드미턴스 및 복소전력)

  • Lee, Jong-Ig
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.13 no.10
    • /
    • pp.2059-2065
    • /
    • 2009
  • In this study, it has been considered that the TEM wave is incident on the transverse slit in the upper plate of a short-ended parallel-plate waveguide (PPW). An equivalent slit admittance and complex power for the case of narrow slit are obtained. The conditions for the slit voltage and the complex power in case of the maximum coupling through the slit with a nearby scatterer exterior the PPW are checked.

Automatic Defect Detection System for Ultra Fine Pattern Chip-on-Film (초미세 패턴 칩-온-필름을 위한 자동 결함 검출 시스템 개발)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2010.05a
    • /
    • pp.775-778
    • /
    • 2010
  • 본 논문에서는 초미세 패턴($24{\mu}m$ 이하의 선폭, $30{\mu}m$ 이하의 피치)을 가진 칩-온-필름(Chip-on-Film, COF)에 발생한 결함을 자동으로 검출할 수 있는 시스템을 제안한다. 개발된 시스템은 COF 패턴으로부터 대표적으로 발생하는 결함들, 즉 개방(open), 단락(hard short), mouse bite(near open) 및 near short(soft short)을 자동으로 신속히 검출할 수 있는 기술이 적용되어 있다. 특히 초미세 패턴의 경우, near open 및 near short과 같은 결함 검출이 불가능한 기존 검출시스템의 문제점을 극복한 기술이 제안되어 있다. 본 논문에서 제안하는 결함 검출 원리는 미세 선의 결함유무에 따른 저항 변화를 자동으로 검출하고, 그 미세한 변화를 좀 더 자세하게 판별하기 위해 고주파 공진기(resonator)를 적용하고 있다. 제안된 시스템은 미세 패턴을 가진 COF 제작 과정에서 발생한 결함을 신속히 검출할 수 있기 때문에 COF 불량 검사에 소요되는 많은 경비를 줄일 수 있으리라 기대한다.

  • PDF

Design of Broadband Planar Yagi Antenna (광대역 평면야기안테나설계)

  • Lee, Jong-Ig;Yeo, Jun-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2010.05a
    • /
    • pp.662-664
    • /
    • 2010
  • In this paper, it is studied that the design method for the planar quasi-Yagi antenna suitable for the operation over 5-10GHz band. Yagi antenna is fed by a short-ended microstrip line and matched by a Balun circuit embedded within the antenna. The results for the characteristics of the Yagi antenna fabricated on the FR4 substrate (${\epsilon}_r$= 4.4, h=0.8mm) agreed well with those predicted by computer simulations.

  • PDF

Answers Candidate Detection System using Dual Pointer Network Decoder (듀얼 포인터 네트워크 디코더를 이용한 정답 후보군 탐지 시스템)

  • Jang, Youngjin;Kim, Harksoo;Kim, Jintae;Wang, Jihyun;Lee, Chunghee
    • Annual Conference on Human and Language Technology
    • /
    • 2019.10a
    • /
    • pp.424-426
    • /
    • 2019
  • 정답 후보군 탐지 모델은 최근 활발히 진행되고 있는 질의-응답 데이터 수집 연구의 선행이 되는 연구로 특정 질문에 대한 정답을 주어진 단락에서 추출하는 작업을 말한다. 제안 모델은 포인터 네트워크 디코더를 통하여 기존의 순차 레이블링 모델에서 처리할 수 없었던 정답이 겹치는 문제에 대해서 해결할 수 있게 되었다. 그리고 독립된 두 개의 포인터 네트워크 디코더를 사용함으로써, 단일 포인터 네트워크로 처리할 수 없었던 정답의 탐지가 가능하게 되었다.

  • PDF

Communication Methodology Between Digital FRTUs Based on Wi-Fi Communication for the Smart Grid of Distribution System Area (스마트 그리드 배전 시스템을 위한 와이파이 통신에 기반한 디지털 FRTU간 통신 방법론 기초연구)

  • Woo-Kyung, Jin;Ji-Hyeon, Youn;Min-Seok, Choi;Jae-Hyun, Lee;Birek, Ohgan;Yun-Seok, Ko
    • The Journal of the Korea institute of electronic communication sciences
    • /
    • v.17 no.6
    • /
    • pp.1113-1120
    • /
    • 2022
  • In this paper, a communication methodology for the digital FRTU(: Feeder Remote Terminal Unit) required by the smart grid distribution system was studied. The digital FRTU consists of a fault handling unit and a communication unit. The fault handling unit transmits fault information to the communication unit in case of a failure, and the communication unit is designed to autonomously determine the fault section through two-way communication between surrounding digital FRTUs. For performance verification, a performance verification system consisting of 3 line sections based on 3 digital FRTUs was constructed to enable fault simulation for various failure scenarios. Various fault cases including one phase ground fault, line-to-line short-circuit fault, and three-phase short-circuit fault were experimentally simulated on the established performance verification system, and the validity of the developed methodology was confirmed by proving the accurate fault section inference results for each fault simulation case.

155.52 Mbps High Performance CMOS Receiver for STM-1 Application (STM-1급 155.52 Mbps 고성능 CMOS 리시버의 구현)

  • 채상훈;정희범
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.24 no.6B
    • /
    • pp.1074-1079
    • /
    • 1999
  • A high performance CMOS receiver for 155.52 Mbps STM-1 digital communication has been designed and fabricated. The ASIC operates properly with 155.52 MHz clock frequency in case of the data loss due to some system error such as transmission line open or data transfer fail. Also it operates properly in case the system starts after the power failure or system maintenance. The designed circuit has especially PLL based self oscillation loop which operates on abnormal environment which is added to main oscillation loop. The measured results show that the circuit operates well with 153.52 MHz clock frequency not only on normal environment but also on abnormal environment. Rms jitter of the PLL loop is about 23 ps.

  • PDF

An Edge Removal Algorithm for the Reliability Evaluation of Directed Communication Networks (방향성 통신망의 신뢰도 계정에 관한 에지제거 알고리즘)

  • 임윤구;오영환
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.13 no.1
    • /
    • pp.63-73
    • /
    • 1988
  • In this paper, an algorithm is proposed to evaluate the source-to-terminal reliability, the probability that a source node can communicate with a terminal node, in a probabilistic derected graph. By using Satyanaratana's factoring $theorem^{(7)}$, the original graph can be partitioned into two reduced graphs obtained by contracting and deleting the edge connected to the source node in the probabilistic directed graph. The edge removal proposed in this paper and the general series-parallel reduction can then be applied to the reduced graph. This edge reduction can be applied recursively to the reduced graphs until a source node can be connected to a terminal node by one edge. A computer program which can be applied to evaluating the source-to-terminal reliability in a complex and large network has also been developed.

  • PDF

Frequency Characteristics of the Return Loss of a Broadband Double-Cone Antenna with Shorting Plate (단락판을 갖는 이중 원추형 광대역 안테나의 반사손실 특성)

  • Jang, Seung-Hoon;Hong, Deok-Gi;Kim, Hyo-gyun;Jung, Sung-Woo;Kim, Ki-Chai
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.27 no.2
    • /
    • pp.101-107
    • /
    • 2016
  • This paper presents the characteristics of a double-cone broadband antenna with compact and three-dimensional structure that can be used in UWB system. The theoretical analysis is conducted using a finite difference time domain(FDTD) method. The parameters are the radius, a height of broadband double-cone antennas with shorting plate, and the number of plates on a ground plane. This paper examines influence of structural parameters on return loss. The results show that a condition for an optimum structure of broadband double-cone antennas with shorting plate exists. It also shows that the broadband double-cone antennas with shorting plate have radiation patterns similar to those of a dipole antenna. To verify the theoretical analysis, computed results are compared to experimental results.

Design of a multi-band antenna for a mobile communication terminal with reconfiguration characteristic (재구성 특성을 갖는 다중대역 이동통신 단말기용 안테나의 설계 및 제작)

  • Im, Dae-Soo;Kim, Ki-Rae;Yoon, Joong-Han
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.19 no.4
    • /
    • pp.772-779
    • /
    • 2015
  • In this paper,a reconfigurable multi-band mobile antenna with switching line for LTE band 13, GSM, K-PCS, WCDMA band. The proposed antenna is planar strip line design and composed of stub shorted to the ground plane and two switching line for proposed band operation. To obtain the optimized parameters, we used the simulator, Using the obtained parameters is fabricated. The numerical and experiment results demonstrated that the proposed antenna satisfied the -6 dB impedance bandwidth requirement while simultaneously covering when the state of sw1 and sw2 on for LTE band 13, the state of sw1 off and sw2 on for GSM, K-PCS, the state of sw1 off and sw2 off for WCDMA. Respectively and characteristics of gain and radiation patterns are determined for a reconfigurable multi-band mobile terminal.

Test Method of an Embedded CMOS OP-AMP (내장된 CMOS 연산증폭기의 테스트 방법)

  • 김강철;송근호;한석붕
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.7 no.1
    • /
    • pp.100-105
    • /
    • 2003
  • In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.