• Title/Summary/Keyword: 텔레메트리

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Telemetry Standard 106-17 LDPC Decoder Design Using HLS (HLS를 이용한 텔레메트리 표준 106-17 LDPC 복호기 설계)

  • Gu, Young Mo;Kim, Seongjong;Kim, Bokki
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.49 no.4
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    • pp.335-342
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    • 2021
  • By using HLS when developing a communication system FPGA, HDL code can be automatically generated from a little modified C/C++ source code used for performance verification, which has the advantage of shortening the development period. In this paper, a method of designing a telemetry standard 106-17 LDPC decoder in C language is proposed using Xilinx's Vivado HLS, and by synthesizing Spartan-7 and Kintex-7 as target devices, throughput and FPGA utilization rate was compared.

Estimation of Thruster Efficiency for Koreasat I, II under APEMAC Operation (무궁화위성1, 2호 APEMAC을 통한 추력기 효율 추정 연구)

  • Park, Young-Woong;Park, Bong-Kyu;Nam, Moon-Gyung;Bang, Hyo-Choong
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.30 no.8
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    • pp.141-147
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    • 2002
  • Estimation of thrusters efficiency is a very important process at the end of lifetime of a satellite. This paper introduces a technique to estimate the efficiency change of thrusters considering bubble effect for Koreasat I. During APEMAC(Automatic Pitch Error/ Momentum Adjust Control), the change in thruster efficiency is estimated to compare the attitude telemetry data of the Koreasat I with the results of the control logic using Simulink. The outcome of this study is expected to contribute to improving the operational load at the end of generic communication satellite mission.

Telemetry Data Recovery Method Using Multiple PCM Data (다중 PCM 데이터를 이용한 텔레메트리 데이터 복구 방법)

  • Jung, Haeseung;Kim, Joonyun
    • Aerospace Engineering and Technology
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    • v.11 no.2
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    • pp.96-102
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    • 2012
  • Recently, interests about frame error reduction method, using multiple PCM data which are received at several ground stations, are increasing. Simple data merge method is already applied to data processing system at Naro Space Center and have been used in the first and the second flight test analysis of KSLV-I. This paper is focused on error reduction with error correcting merge algorithm and time-delayed data correction algorithm. Result of applying the proposed algorithms to the flight test data shows 1.32% improvement in error rate, compared to simple-data-merge method. It is considered that presented algorithms could be very useful in generating various telemetry merge data.

Attitude analysis induced by the disturbances on COMS using the received telemetries during normal mode (정상모드에서 수신된 텔레메트리를 이용한 외란에 의한 천리안위성 자세영향 분석)

  • Park, Young-Woong;Park, Bong-Kyu
    • Aerospace Engineering and Technology
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    • v.11 no.1
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    • pp.27-41
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    • 2012
  • In this paper, there is analyzed the disturbances to impact on COMS attitude and the attitude error using the received telemetries in KARI ground station during normal mode of COMS. COMS was launched successfully at Kourou, French Guiana on the 26th of June, 2010. Up to now after IOT(in-orbit test), COMS is performing well the main mission to measure meteorology and ocean during about half and one year. The disturbances to impact on COMS attitude are mostly by the Sun, by the motion of payload mirror and by the spike happened during operation of earth sensor mirror and wheel. The analysis result on the other cases happened rarely during the nominal operation, is summarized.

Telemetry Standard 106-17 LDPC Encoder Design Using HLS (HLS를 이용한 텔레메트리 표준 106-17 LDPC 부호기 설계)

  • Gu, Young Mo;Lee, Woonmoon;Kim, Bokki
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.48 no.10
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    • pp.831-835
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    • 2020
  • By automatically generating HDL codes from C/C++ source codes, HLS makes it possible to shorten FPGA system developing period through easy timing control and structure change. We designed LDPC encoder for telemetry standard 106-17 with Xilinx Vivado HLS and showed hardware structure can be easily adapted for different purposes through minor C code modification. Synthesis results targeting Spartan-7 xc7s100 device are presented for throughput and hardware complexity comparison.

Phase Locked Loop based Time Synchronization Algorithm for Telemetry System (텔레메트리 시스템을 위한 PLL 기반의 시각동기 알고리즘)

  • Kim, Geon-Hee;Jin, Mi-Hyun;Kim, Bok-Ki
    • Journal of Advanced Navigation Technology
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    • v.24 no.4
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    • pp.285-290
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    • 2020
  • This paper presents a time synchronization algorithm based on PLL for application to telemetry systems and implement FPGA logic. The large aircraft of the telemetry system acquires status information through each distributed acquisition devices and analyzes the flight status in real time. For this reason, time synchronization between systems is important to improve precision. This paper presents a PLL based time synchronization algorithm that is less complex than other time synchronization methods and takes less time to process data because there is minimized message transmission for synchronization. The validity of proposed algorithm is proved by simulation of Python. And the VHDL logic was implemented in FPGA to check the time synchronization performance.

Implementation of Wavelet Transform for a Real time Monitoring ECG Telemetry System (웨이브렛 변환을 이용한 실시간 모니터링 ECG 텔레미트리 시스템 구현)

  • 박차훈;서희돈
    • Journal of the Institute of Convergence Signal Processing
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    • v.3 no.1
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    • pp.27-32
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    • 2002
  • In this study, we fabricated the advanced telemetry system that transmitting media use radio frequency(RF) for the middle range measurement of the physiological signals and receiving media use optical for electromagnetic interference problem. The telemetry system within a size of 65$\times$125$\times$45mm consists of three parts: RF transmitter, optical receiver and physiological signal processing CMOS one chip. Advantages of proposed telemetry system is wireless middle range(50m) FM transmission, reduce electromagnetic interference to a minimum which enables a comfortable bed-side telemetry system. The monitoring system was designed in the structure of dual-processor for the real time processing. The use of the one channel in our study made it possible the real time wavelet transformation of electrocardiogram data of 360Hz, 16 bits for every 1.42 seconds.

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SOQPSK-TG Receiver Using Trellis State Combining (트렐리스 상태 결합을 이용한 SOQPSK-TG 수신기)

  • Gu, Young Mo;Boo, Jungil;Kim, Bokki
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.47 no.3
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    • pp.240-244
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    • 2019
  • SOQPSK-TG which consists of differential precoder and CPM modulator was adopted as telemetry standard because of its high power and bandwidth efficiency. We proposed four-state Viterbi decoder for SOQPSK-TG. Reducing the trellis state to four was possible by simplifying frequency pulse of SOQPSK-TG to square pulse of symbol length 2 and combing this with differential precoder. Compared with conventional SOQPSK-TG receivers, computer simulation result shows about 1 dB performance improvement was achieved at BER of $10^{-5}$ in AWGN channel.