• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.114-125
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• 2014

In a conventional sonar system, which uses LFM signal for detecting targets with varying speed, the results of multiple LFM Doppler correlators are aligned and the maximum alined result are selected as a test cell for detecting targets. As the number of the LFM Doppler correlators are increased for accurate target detection, as the required computational complexity and the memory are also increased. This fact makes it difficult to implement the accurate LFM target detector. In this paper, we propose a new fast target detection which is robust for the variation of target speed. Because the proposed method uses the summation of alined results of large numbers of LFM Doppler correlators, the proposed method increase SNR and provide robust SNR for the variation of target speed. And the proposed method can provide very fast target detection by implementing the process, the summation of alined results of large numbers of LFM Doppler correlators, as one summation filter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.74-83
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• 2002

In order to design a huge VLSI system, the scan testing methodology by employing scan flip-flops(cells) is a popular method to test those If chips. In this case, the connection order of scan cells are not important, and hence the order can be determined in the very final stage of physical design such as cell placement. Using this fact, we propose, in this paper, a scan cell reordering method which minimizes the length of wires for scan chain connections. Especially, our reordering method is newly proposed method in the case when the scan cells are grouped according to their clock domains. In fact, the proposed reordering method reduces the wire length about 13.6% more than that by previously proposed reordering method. Our method may also be applicable for reordering scan chains that have various constraints on the scan cell locations due to the chain grouping.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Korean Journal of Optics and Photonics
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• v.9 no.6
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• pp.417-422
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• 1998

In this paper we introduce a method to optimize panel parameters and drive signals in a matrix-adressed bistable twsited-nematic (BTN) liquid crystal display (LCD) panel. We measured the effect of data pulses on optical switching characteristics in a BTN LC cell to model the effect theoretically. We introduce a weighting function to model the effect of data pulses on the switching energy as a function of time. Once the weighting function is known, we can estimate the maximum number of lines for multiplexing operation at a given frame rate by calculating the minimum data pulse width. By characterizing a unit cell as we change panel parameters (for example, d/p ratio), we can optimize parameters for high-speed operation. We found that our theoretical predictions agree very well with experimental results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.30-37
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• 2006

This paper presents a modified scan cell architecture to reduce the power dissipation during testing. It not only eliminates switching activities in the combinational logic during scan shifting but also reduces switching activities in the scan chain during the time. Furthermore, it limits the transitions on capture cycles. It can be made for test-per-scan BIST and employed in both single scan style and multiple scan style. Experimental results demonstrate that the proposed structure achieves the same fault coverage with lower power consumption compared to other existing BIST schemes.

• Journal of the Korea Society of Computer and Information
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• v.11 no.4 s.42
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• pp.291-297
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• 2006

This paper presents a new anti-copying methode for hard copy documents. The approach protects the document and its content from unauthorized copying and forgeries, while using ordinary paper and ordinary printer. The paper copy is protected against copying as the photocopy version will appear differently when compared to the authorized printed original hard copy using Human Visual System. The anti-copying pattern created through pointillism with a halftone cell and a spot. The proposed method is useful for unauthorized copying and forgeries with high-resolution scanners and photocopiers.

• 한국HCI학회:학술대회논문집
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• 2006.02b
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• pp.191-196
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• 2006

새로운 휴대폰 기기가 하루가 다르게 개발되어 상품화 되는 가운데 사용자의 시각에 입각한 사용성 평가는 앞으로 새롭게 선보일 휴대폰 기기의 방향성을 제시해 줄 수 있는 중요한 척도이다. 특히 근 몇 년간 다양한 기능이 convergence 된 휴대폰들이 늘어남에 따라 사용자 관점에서의 평가 방법에 있어, 실제 사용자는 예측할 수 없고 셀 수 없는 다양한 상황과 환경 속에서 휴대폰 기기를 사용하게 된다는 사실을 주목해야 할 것이다. 따라서 본 연구에서는 끊임없이 변화하는 휴대폰 기기로 인하여 실제 user 가 자신의 특성과 습관, 시시각각 다르게 처하는 환경과 함께 야기되는 휴대폰에 대한 use experience 를 수집하고 분석하는 적합한 방법론을 새로이 제시하고, 이를 사례 연구를 통하여 검증함으로써 사용자 경험을 수집하는데 유용한 새로운 방법론을 개발하는데 그 목적이 있다. 이러한 사용성 테스트의 새로운 분석 방법으로, 특정 휴대폰의 웹 리뷰사이트, 인터넷 동우회와 같은 온라인 커뮤니티상에서 테스트에 응할 여지가 있는 expert user 를 엄선하여 선정 하였으며, 그들에게 휴대폰을 사용하면서 겪게 되는 경험이나 문제점을 휴대폰의 어떠한 부분에서 언제, 어떠한 식으로 발생되었는지에 대하여 work book 의 형식을 통하여 기록하고 다시 그것을 바탕으로 In-depth interview 함으로써 사용자의 경험의 축적에 따라 사용성을 평가하는 프로세스를 새로이 개발하고 적용하였다.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.21 no.3
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• pp.29-35
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• 2022

When a vehicle is driven off a road surface, the deformations of the road surface and tire are combined. Consequently, the dynamic behavior of wheel movement becomes difficult to predict and control. Herein, we propose a tire test bed to capture the dynamic behavior of tires moving on sand and soil. Based on this study, it is discovered that the slip rate can be controlled, and the vertical force can be measured using a load cell. The test results show that this test bed can be useful for capturing the dynamic behavior of the tire and validating dynamic simulations. In fact, the tire test bed developed in this study can be used to verify the results of computer simulations. In addition, it can be used for basic experiments pertaining to the speed control of unmanned autonomous vehicles.

• Transactions of the Korean hydrogen and new energy society
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• v.22 no.6
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• pp.842-851
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• 2011

A multi-cell test system with 25 independent cells is used to test different electrode materials simultaneously for polymer electrolyte membrane fuel cells (PEMFCs). Twenty-five segmented membrane electrode assemblies (MEAs) having the same or different Pt-loading are prepared to analyze the performance deviation of cells in the multi-cell test system. Improvements in the multi-cell test system are made by ensuring that the system performs voltage sensing for the cells individually and inserting optimum gaskets between the MEAs and the graphite plates. The cell performances are improved and their deviations are significantly decreased by these modifications. The performance deviations changed according to various cell configurations because the operating conditions of the cells, such as the gas flow and concentration, differed. This cell system can be used to test multiple electrodes simultaneously because it shows relatively uniform performance under the same conditions as well as linear correlation with various catalyst loadings.