• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.706-708
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• 2005

MMORPG게임의 구현에 있어서 가장 큰 문제의 하나는 서버와 연결된 클라이언트들 사이의 동기화이다. 이를 위해서 MMORPG게임에서는 grid-based filtering을 적용하여 동기화 문제를 해결하고 있다. 그러나 MMORPG게임의 형태가 이인칭 관점 시점의 2D에서 일인칭 관점의 시점의 3D 게임으로 변함에 따라서 grid-based filtering으로 인한 동기화는 낭비적인 요소를 포함하게 되었다. 즉 일인칭 관점시점의 3D게임에서는 가까운 거리의 캐릭터 사이에도 주변 장애물의 영향으로 비 가시관계에 놓임에 따라서 동기화의 필요성이 없어지는 경우가 생기게 된다. 따라서 본 논문에서는 일인칭 관점 게임의 3D MMORPG게임에서 컴파일 시 각 셀을 중심으로 가시성 테스트를 수행하여 가시영역내의 셀들만을 동기화 대상으로 지정한 후 게임 진행 시 현재 셀 속의 캐릭터들에게 동기화 대상으로 설정된 셀 속의 클라이언트들만을 동기화 시켜줌으로서 통신량을 줄여주는 방법을 제안한다.

• The Journal of the Korea Contents Association
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• v.5 no.4
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• pp.188-196
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• 2005

This paper presents a new test data compression and low power scan test method that can reduce test time and power consumption. A proposed method can reduce the scan-in power and test data volume using a modified scan cell reordering algorithm and hybrid adaptive encoding method. Hybrid test data compression method uses adaptively the Golomb codes and run-length codes according to length of runs in test data, which can reduce efficiently the test data volume compare to previous method. We apply a scan cell reordering technique to minimize the column hamming distance in scan vectors, which can reduce the scan-in power consumption and test data. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases. The proposed method showed an about a 17%-26% better compression ratio, 8%-22% better average power consumption and 13%-60% better peak power consumption than that of previous method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.15-22
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• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.449-449
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• 2012

플라즈마 디스플레이 패널(PDP)은 가격 경쟁력이 뛰어나고 빠른 반응 속도를 기반으로 한 생생한 화질이 구현 가능한 장점에 힘입어 대형 평판 디스플레이 시장에서 주도적인 위치를 점하여 왔다. 이러한 특징을 갖고 있는 PDP는 최근 성장세를 보이고 있는 PID (Public Information Display) 시장에서도 그 효력을 발휘할 것으로 보인다. 따라서 기존의 HD급이나 Full HD급 미소 방전셀이 아닌 대면적 방전셀을 적용한 PDP 의 방전 특성에 대한 연구가 중요할 것으로 생각된다. 본 논문에서는 ITO 전극 간격 및 전극 폭, 격벽의 폭 및 높이 등 PDP 의 방전 특성에 영향을 미치는 요소들의 수치를 변화시켜 가며 대면적 방전셀을 적용한 PDP의 기본적인 방전 특성을 살펴보고자 하였다. 이를 바탕으로 대면적 방전셀 PDP에서 고효율을 달성하기 위해 필요한 인자의 설계 방향을 제시해보고자 하였다. 본 논문에서 연구된 PDP는 0.862.58 mm의 셀의 크기를 갖도록 설계하였다. 앞서 제시한 바와 같이 구조 변수의 최적화를 위하여 ITO 전극 간격은 80~1, 전극의 폭은 250~750로 다양하게 주어 상판을 제작하였고 격벽의 폭은 100~200, 높이는 150~300까지 다양한 크기를 가지는 하판을 제작하여 박막 증착, 합착, 가열 배기 등의 과정을 통하여 최종적으로 2인치 크기의 테스트 패널을 제작하여 각 패널별 전압 변화, 휘도, 효율 특성 등이 분석되었다. 실험 결과 격벽 폭 150, 높이는 300일 때 negative glow 방전이 안정적으로 형성될 수 있었음을 확인하였고 최적화된 격벽 수치를 기반으로 다양한 ITO 전극 간격 및 전극 폭을 적용한 패널의 방전 특성을 분석할 수 있었다. 이러한 일련의 실험 결과들을 기반으로 향후 대면적 방전셀의 방전 전압을 낮추고 발광 효율을 개선하는데에 있어서 3전극의 면방전 구조를 가지는 PDP 의 셀을 설계하는데에 있어서 올바른 방향을 마련할 수 있을 것이라 생각된다.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2010.11a
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• pp.339-342
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• 2010

Doosan Heavy Industries & Construction Co., Ltd. constructed a gas turbine engine test cell to verify operating characteristics and design parameters of 5MW class gas turbine engine for power generation under developing. Engine test cell was designed to satisfy critical requirements to scrutinize all performance parameters of the engine with safe and reliability in accordance with design specification. As the test cell developed can effectively reproduce engine operation conditions covering from start-up to maximum power condition, it can be utilized to make a continuing design improvement of the engine based on practical test data at full stretch. Moreover, it is expected to be serviceable to develop derivative engines and be utilized to put them into serial production and contribute to a competitiveness reenforcement as a gas turbine engine manufacturer.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.4
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• pp.401-410
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• 2001

An adaptive Odd/Even Multi-shell Median Filter(Adaptive O/E MMF) is proposed by using a adaptive threshold strategy and odd/even multishells. This algorithm was verified in MATLAB and implemented on FPGA. The performance of the algorithm is evaluated by adding impulse noise and line missing into well-known images. A proposed adaptive threshold strategy may reduce the computation time and redundant arrangement. odd and even multishells can recover line missing of vertical and diagonal directions respectively Therefore, the algorithm proposed in this work can be effectively used in real time image processing applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1424-1433
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• 2007

In this paper, we propose a hardware architecture to generate digital hologram using the modified CGH (Computer Generated Hologram) algorithm for hardware implementation and design to FPGA (Field Programmable Gate Array) platform. After analyzing the CGH algorithm, we propose an architecture of CGH cell which efficiently products digital hologram, and design CGH Kernel from configuring CGH Cell. Finally we implement CGH Processor using CGH Kernel, SDRAM Controller, DMA, etc. Performance of the proposed hardware can be proportionally increased through simply addition of CGH Cell in CGH Kernel, since a CGH Cell has operational independency. The proposed hardware was implemented using XC2VP70 FPGA of Xilinx and was stably operated in 200MHz clock frequency. It take 0.205 second for generating $1,280{\times}1,024$ digital hologram from 3 dimensional object which has 40,000 light sources.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2123-2135
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• 1997

In this paepr, we consider resistive shorts on drain-source, drain-gate, and gate-source as well as opens in MOSFETs included in typical memory cell of VLSI SRAM. Behavior of memeory is observed by analyzing voltage at storage nodes of memeory and IDDQ(quiescent power supply current) through PSPICE simulation. Using this behavioral analysis, an effective testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ testing simultaeously is proposed. Built-In Self Test(BIST) circuit which detects faults in memories and Built-In Current Sensor(BICS) which monitors the power supply bus for abnormalities in quescent current are developed and imprlemented to improve the quality and efficiency of testing. Implemented BIST and BICS circuits can detect locations of faults and defects in order to repair faulty memories.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.74-84
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• 2003

Conventional test algorithms do not effectively detect faults by word-line and bit-line coupling noise resulting from the increase of the density of memories. In this paper, the possibility of faults caused by word-line coupling noise is shown, and new fault model, WLSFs(Word-Line Sensitive Fault) is proposed. We also introduce the algorithm considering both word-line and bit-line coupling noise simultaneously. The algorithm increases probability of faults which means improved fault coverage and more effective test algorithm, compared to conventional ones. The proposed algorithm can also cover conventional basic faults which are stuck-at faults, transition faults and coupling faults within a five-cell physical neighborhood.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.48-55
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• 1998

In this work, the testable CAM(Content Addressable Memory) is designed to perform the test effectively by inserting the ECC(Error Checking Circuit) inside the CAM. The designed CAM has the circuit which is capable of testing the functional faults in read, write, and match operations. In general the test circuit inserted causes the increase of total circuit area, Thus this work, utilizes the new MTA code to reduce the overhead of an area of the built-in test circuit which has a conventional parallel comparator. The designed circuit was verified using the VHDL simulator and the layout was performed using the 0.8${\mu}{\textrm}{m}$ double metal CMOS process. About 30% reduction of a circuit area wad achieved in the proposed CAM using the XOR circuit