• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2154-2162
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• 2009

This paper describes a scalar multiplier for Elliptic curve cryptography for smart card security. The scaler multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scala multiplication on finite field, the non-adjacent format (NAF) conversion algorithm which is based on complementary recoding is adopted. The scalar multiplier core synthesized with a 0.35-${\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smartcard security.

• Annual Conference of KIPS
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• 2004.05a
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• pp.1157-1160
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• 2004

현재 사용되고 있는 대부분의 메신저는 서버에 로그 온할 때 패스워드를 RC5등으로 암호화해서 보내지만 패스워드 크래킹 프로그램들이 많이 알려져 있어 안전하지 못하다. 또한 로그 온한 후 통신하는 두 호스트들 간의 전송되는 정보가 아무런 보호 장치 없이 네트워크를 통해 전송되어 제3자에 의한 도청이 가능하게 된다. 따라서 전송되는 정보의 암호화를 포함하는 안전한 메신저 서비스의 필요성이 대두되고 있다. 본 논문에서 제안된 안전한 메신저는 동일한 키 사이즈를 갖는 다른 공개키 암호체계보다 훨씬 강하다고 알려져 있는 타원곡선 암호체계를 이용하여 빠르고 효율적이며 높은 안전도를 나타내는 패스워드 키 교환 방식을 설계하였고, 사용자간에 IPSec프로토콜을 사용하여 효율적인 데이터 전송이 가능하고 또한 보안성을 높이기 위한 방법으로 Host-to-Host간의 데이터가 인터넷에서 가상의 파이프를 통해 전달되도록 터널 모드를 제시하였다.

• Annual Conference of KIPS
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• 2010.11a
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• pp.1213-1216
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• 2010

인터넷을 통한 IT환경의 변화로 개인정보를 이용한 다양한 서비스들이 등장하게 되었고, 이에 따라 개인정보보안의 중요성이 증대되고 있다. 정당한 사용자를 확인하는 인증기술의 발달로 한 세션에서 패스워드 값을 사용 후 폐기하는 일회용 패스워드에 관한 연구가 활발히 진행되고 있다. 그러나 기존의 일회용 패스워드는 기밀성, 상호인증, 연산량 등 여러 문제점을 내포하고 있다. 따라서 본 논문에서는 이러한 기존의 일회용 패스워드의 문제점을 분석하고 이를 해결하기 위해 타원곡선 암호 알고리즘을 이용한 일회용 패스워드 생성 기법에 관하여 제안하였다. 제안방식은 암호 알고리즘을 이용하여 기밀성을 제공하며, 서버와 클라이언트 간의 상호인증을 제공할 수 있도록 하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1998.12a
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• pp.231-242
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• 1998

전자 상거래에 대한 다양한 프로토타입(prototype)이 구현되고 있고, 확대 적용의 현실성이 증대되고 있는 작금의 상황을 반영하여 관련 연구가 활발해지고 있으며, 그 중에서 보다 안전하고 효율적인 전자지불방식에 대한 현실적 요구가 증대하고 있다 전자지불방식의 하나인 전자화폐는 실물 화폐와 유사한 성질들을 만족해야 하며, 이러한 성질들 중에서 필수적인 익명성을 얻기 위한 방법으로는 D. Chaum이 제안한 Blind Signature가 대표적이다. 본 논문에서는 기존의 암호시스템의 문제점을 극복할 수 있는 시스템으로써 주목받고 있는 타원곡선 암호시스템 상에서 익명성을 제공하는 Blinding ECDSA를 제안한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.656-658
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• 2013

Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to the design of an elliptic curve crypto-engine server farm. I successfully implemented the whole system including the test bench in one integrated environment, otherwise in the traditional way it would have cost Verilog simulation and C/SystemC verification which means much more time and effort.

• Journal of KIISE:Information Networking
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• v.29 no.4
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• pp.333-345
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• 2002

As computers and networks become popular, distributing information on the Internet is common in our daily life. Also, the explosion of the Internet, of wireless digital communication and data exchange on Internet has rapidly changed the way we connect with other people. But secure mail is gaining popularity abroad and domestically because of their nature of providing security. That is. It has been used a variety of fields such as general mail and e-mail for advertisement. But, As the data transmitted on network can be easily opened or forged with simple operations. Most of existing e-mail system don't have any security on the transmitted information. Thus, security mail system need to provide security including message encryption, content integrity, message origin authentication, and non-repudiation. In this paper, we design and implement secure mail system with secure key agreement algorithm, non-repudiation service, and encryption capability to provide services for certification of delivery and certification of content as well as the basic security services.

• Annual Conference of KIPS
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• 2021.11a
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• pp.232-235
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• 2021

동형암호는 서버에 암호화된 데이터를 통해 연산할 수 있다는 장점으로 대용량의 데이터를 암호화하여 처리하는 시스템에 사용될 수 있어 주목된다. 동형암호의 방법 중 효율성과 실용성을 지니는 장점으로 인해 연구되고 있는 Bilinear Pairing을 사용하는 서명 및 인증 방법들은 DDH와 CDH 문제에 기반을 둔 방법으로, 많은 연구가 진행되어 왔다. 본 논문은 동형암호에서 사용되는 Bilinear Pairing의 핵심인 GDH 그룹과 타원곡선암호, Weil Pairing, SDH 문제를 기반으로 하는 서명 방식과 그룹 서명 방식, 랜덤오라클을 제외한 서명을 소개한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.39-44
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• 2009

The advance of communication and networking technology enables high bandwidth multimedia data transmission. The development of high performance compression technology such as H.264 also encourages high quality video and audio data transmission. The trend requires efficient protection system for digital media rights. We propose an efficient digital media protection system using elliptic curve cryptography. Only key parameters are encrypted to reduce the burden of complex encryption and decryption in the proposed system, and the digital media are not played back or the quality is degraded if the encrypted information is missing. We need a playback system with an ECC processor to implement the proposed system. We implement an H.264 decoding system with a configurable ECC processor to verify the proposed protection system We verify that the H.264 movie is not decoded without the decrypted information.