• Journal of Platform Technology
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• v.12 no.2
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• pp.34-44
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• 2024

This paper proposes a dynamic clock supply control algorithm and a system load power stabilization algorithm that minimizes the power consumption of the sensing system, which accounts for the largest percentage of power consumption in mobile devices, to extend the usage time of the rechargeable battery mounted on the mobile device. The dynamic clock supply control algorithm can reduce the power consumed by the sensing system by configuring a circuit to cut off the power of the sensing system and by recognizing the state of low sensor change and adjusting the measurement cycle. The system load power stabilization algorithm is an algorithm that controls the power of the surrounding module according to the power consumption state, and when it requires a lot of power, it controls the clock supply to stabilize the operation. The experimental results confirmed that applying only the dynamic clock supply control algorithm reduces the power consumed by the sensing system by 17%, and applying only the system load power stabilization algorithm reduces power consumption by 9.3%, enabling it to operate stably in situations that require a lot of power such as image processing. When both algorithms were applied, the power consumption of the battery was reduced by 67% compared to before applying the algorithm. Through this, the reliability of the proposed method was confirmed.

• The KIPS Transactions:PartC
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• v.16C no.1
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• pp.51-56
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• 2009

Time synchronization algorithm in wireless sensor networks is essential to various applications such as object tracking, data encryption, duplicate detection, and precise TDMA scheduling. This paper describes CDRS that is a time synchronization algorithm using the Clock Drift rate and Reference Signals between two sensor nodes. CDRS is composed of two steps. At first step, the time correction is calculated using offset and the clock drift rate between the two nodes based on the LTS method. Two nodes become a synchronized state and the time variance can be compensated by the clock drift rate. At second step, the synchronization node transmits reference signals periodically. This reference signals are used to calculate the time difference between nodes. When this value exceeds the maximum error tolerance, the first step is performed again for resynchronization. The simulation results on the performance analysis show that the time accuracy of the proposed algorithm is improved, and the energy consumption is reduced 2.5 times compared to the time synchronization algorithm with only LTS, because CDRS reduces the number of message about 50% compared to LTS and reference signals do not use the data space for timestamp.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.825-827
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• 2010

본 논문에서는 여러 스테레오 매칭 알고리즘에서 차이값 생성에 사용되는 SAD(Sum of Absolute Differences)의 윈도우 기반 하에서 효율적인 수행에 관해 제시한다. 본 $8{\times}8$ 윈도우 기반의 SAD는 데이터 입력 상태와 데이터 쉬프트 상태로 나뉜다. 데이터 쉬프트 상태에서 디스패리티가 $8{\times}8$ 개의 데이터가 한 클럭에 한번에 생성이 되며 쉬프트 동작으로 데이터 코스트의 연속적인 생성이 가능하다. 본 논문에서는 $8{\times}8$ 윈도우 기반의 SAD를 설계하고 검증한다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.39-48
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• 2009

Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2001.05a
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• pp.77-83
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• 2001

In recent years, the AES in North America and the NESSIE project in Europe have been in progress. Six proposals have been submitted to the NESSIE project including the LILI-128 by Simpson in Australia in the synchronous stream cipher category. These proposals tend towards a design with parallelism of the algorithms in order to facilitate speed-up. In this paper, we consider the PS-LFSR and propose the effective implementation of various nonlinear combiners: memoryless-nonlinear combiner, memory-nonlinear combiner, nonlinear filter function, and clock-controlled function. Finally, we propose m-parallel SUM-BSG and LILI-l28's parallel implementation as examples, and we determine their securities and performances.

• The KIPS Transactions:PartC
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• v.16C no.2
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• pp.229-236
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• 2009

UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area networks. The clock frequency differences of nodes have serious affects on asynchronous ranging methods to estimate locations of mobile nodes. The specification of high rate UWB describes successive TWR method with the estimation of a relative clock frequency offset. In this paper, we complete the ranging equations using relative frequency offset and time information, and propose a method to estimate the exact frequency offsets. We evaluate the ranging algorithms with simulation. The results show that the performances of the algorithms using frequency offsets are very close without noise. But, at noise environment, the method of exact frequency offsets shows better performance than that of relative frequency offsets.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.1002-1005
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• 2015

Mobile operating systems have been typically classified into Apple and Android. Samsung showed its own new mobile OS developing Tizen based on Linux kernel. Mobile operating system has developed a technology using low-power by itself because of the limitation of capacity of battery, a feature of mobile. Samsung Tizen OS has a low-power technology called Power Manager controling LCD states as users'inputs or time-out events occur. However, if users'input occurs frequently, energy consumption jumped before-and-after users'input because CPU clock is increased rapidly due to overhead increase for frequent LCD state changes. This paper proposes a mechanism to reduce the overhead for LCD state changes, when user's input is frequent, by adding a new state to the Power Manager the current Tizen OS is using. We have implemented the proposed mechanism at Tizen phone kernel layer in this paper and experimented the mechanism according to users' LCD touch inputs. The experiment shows that it is possible to decrease energy by reducing the CPU clock increase according to the frequent user's inputs.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.292-295
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• 2003

블루투스 전송 기술은 2.4㎓ 의 ISM(Industrial Scientific Medicine)밴드에서 주파수 호핑 방식을 사용한다. 주파수 호핑율은 연결 상태에서 초당 1600회, 조회 또는 호출 상태에서 초당 3200회의 호핑을 한다. Hop 채널 선택은 블루투스 표준안에서 제시한 5개의 호핑 시퀸스 중 하나를 선택하고 호핑 주파수에 따라 이를 매핑 함으로써 이루어진다. 본 논문에서는 6개의 상태에 따라 다르게 실행되는 채널 계산을 효율적으로 제어하고 필요한 연산모듈의 수를 줄이기 위해 9비트 프로세서를 이용해 Hop 선택 모듈을 설계하고 구현한다. 설계된 모듈은 레지스터 파일, 마이크로프로그램 제어장치, 가산, 치환(permutation), Modulo 계산을 위한 3개의 연산장치로 구성된다. Hop 채널 계산 중 가장 클럭 소요가 큰 Modulo 연산은 SRT나눗셈 알고리즘을 사용하여 음수 값 계산 및 연산 속도 향상을 꾀하였다. 제시된 Hop 선택 모듈은 하드웨어 묘사언어인 VHDL로 설계하고 시뮬레이션 및 테스트는 Xilinx FPGA를 이용해 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.55-62
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• 2000

This paper presents an analysis of the chaotic behavior in the discrete-time voltage mode chaotic generator fabricated using 0.8${\mu}{\textrm}{m}$ single poly CMOS technology. An approximated empirical equation is extracted from the measurement data of a nonlinear function block. Then the bifurcation diagram is simulated according to input variables and Lyapunov exponent λ which represent a dependence on an initial value is calculated. We show the interrelations among time waveforms, state transition, and power spectra for the state condition of chaotic circuit, such as equilibrium, periodic, and chaotic state. And results of experiments in the chaotic circuit with the $\pm$2.5V power supply and sampling clock frequency of 10KHz are shown and compared with the simulated results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.