• Title/Summary/Keyword: 코어길이

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Experimental Study on Characteristics of Micro-Supersonic Jet Flows (마이크로 초음속 제트유동 특성에 관한 실험적 연구)

  • Kim, Jong-Hun;Bang, Jin-Young;Lee, Yeol
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.36 no.8
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    • pp.774-779
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    • 2008
  • An experimental study on the micro-supersonic jet flow fields has been carried out. A sonic nozzle of 440 ${\mu}m$-exit diameter and a Laval nozzle of 800 ${\mu}m$ exit diameter with the nozzle exit Mach number 2.0 were fabricated by stretching a micro Pyrex glass tube for the present experiments. Schlieren flow visualization and Pitot pressure distribution of the jet flow field were obtained. Representative characteristics of the jet flow fields such as, supersonic length, jet core length, similarity of the velocity field, and jet spreading rates, have been observed. All the results were compared to previous observations of larger supersonic jets of higher Reynolds numbers, and it was found that overall characteristics of the micro supersonic jet are qualitatively similar as those of the higher Reynolds number jets, except the jet core length and the jet spreading rate.

FPGA Implementation of ARIA Encryption/Decrytion Core Supporting Four Modes of Operation (4가지 운영모드를 지원하는 ARIA 암호/복호 코어의 FPGA 구현)

  • Kim, Dong-Hyeon;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.237-240
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    • 2012
  • This paper describes an implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-core supports three master key lengths of 128/192/256-bit specified in the standard and the four modes of operation including ECB, CBC, CTR and OFB. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. The ARIA crypto-core is verified by FPGA implementation, the estimated throughput is about 1.07 Gbps at 167 MHz.

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A Study on the Design and Effect of Feedback for Virtual Reality Exercise Posture Training (가상현실 운동 자세 트레이닝을 위한 피드백 설계 및 효과 연구)

  • Park, Woohee;Kim, Jieun;Lee, Jieun
    • Journal of the Korea Computer Graphics Society
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    • v.26 no.3
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    • pp.79-86
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    • 2020
  • It is important to exercise in the correct posture in order to increase the exercise effect of the core exercise. This paper introduces a system that can train an exercise posture by providing feedback so that a user who performs core exercise in a virtual reality environment can take an accurate posture. It targeted three core movement postures, such as squat, lunge, and bridge, and provides visual feedback and haptic feedback to the user to take an accurate posture. The reference posture is generated by adjusting the expert's posture to the user's body length, and the accuracy of the exercise posture is calculated by comparing the user's posture with the reference posture. The effectiveness of the feedback was verified through user experiments, and the training effects according to the design of the feedback were compared.

Fundamental Experiment to Verify the Resolution of Hetero-core Fiber Optic Sensor for the Prestress Measurement (프리스트레스 측정을 위한 헤테로코어 광파이버 센서의 분해능 검증 기초실험)

  • Park, Eik-Tae;Choi, Kwang-Su;Kim, Tae-Yang;Lee, Hwan-Woo
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.31 no.5
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    • pp.259-266
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    • 2018
  • This is the study for developing the hetero-core optical fiber sensors which are purpose to measure the prestress of PSC bridges during the life cycle period. The goal of this study is to improve the resolution of hetero-core sensors. As a result of the test, it is possible to measure the displacement in $2{\mu}m$ increments. In other words, if the length of the sensor module is 30cm, it is possible to measure the prestress variations in 0.2MPa increments at specified compressive strength of concrete(fck) of 40MPa by Hook's Law. So it can be useful for development of a sensor module measuring internal prestress measurement.

A Cortex-M0 based Security System-on-Chip Embedded with Block Ciphers and Hash Function IP (블록암호와 해시 함수 IP가 내장된 Cortex-M0 기반의 보안 시스템 온 칩)

  • Choe, Jun-Yeong;Choi, Jun-Baek;Shin, Kyung-Wook
    • Journal of IKEEE
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    • v.23 no.2
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    • pp.388-394
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    • 2019
  • This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.

A Design of Security SoC Prototype Based on Cortex-M0 (Cortex-M0 기반의 보안 SoC 프로토타입 설계)

  • Choi, Jun-baek;Choe, Jun-yeong;Shin, Kyung-wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2019.05a
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    • pp.251-253
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    • 2019
  • This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

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Field Analysis in the Ferrite Core at 100 kHz Band Magnetic Field (100 kHz 대역의 자계 환경내(內)에서의 페라이트 코어의 계(界) 해석)

  • Koo, Bon-Chul;Yoo, Jae-Sung;Kim, Mi-Ja;Gimm, Yoon-Myoung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.8
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    • pp.977-983
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    • 2007
  • Recently, the number of systems which utilize wireless power transmission to a receiving module in a short distance is increasing. For efficient use of receiving space, coils are wound around the ferrite core to produce electromotive force(emf) in suppling power by wireless transmission. This paper analyzed the magnetic flux density distribution in the ferrite core in magnetic field environment which is uniformly oriented along to a single axis at 125kHz. For numerical analysis, Ansoft Maxwell which is applying the FEM(Finite Element Method) method was used. We studied the variations of the gathered magnetic fluxes to the changes of the relative permeabilities of the ferrite cores. Also we calculated the magnetic flux variation by shaving the ferrite core off for the groove of coil winding. Results showed that using a small ferrite core in magnetic field at 100kHz band can increase the amount of magnetic flux $3{\sim}4 times$ than without the core. The magnetic flux decreased 23% by shaving the core 0.5 mm on the periphery of 4.75 mm radius core with the relative permeability 800.

X-ray propagation in photonic crystal structured X-ray waveguides (광자결정 구조를 갖는 X-선 도파로에서 X-선 도파현상)

  • 윤형근;김진채;이병하;최재호;박영한
    • Proceedings of the Optical Society of Korea Conference
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    • 2002.07a
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    • pp.164-165
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    • 2002
  • 광자결정 광섬유(photonic crystal fiber)는 주기적으로 배열된 공기기둥이 광섬유의 길이 방향으로 정렬되어 일반광섬유의 크래팅의 역할을 하고 있고 코어는 이들 공기구멍의 중심부에 인위적인 결함을 만들어 광도파가 가능하게 된다 이러한 광자결정 광섬유의 광학적 특성은 넓은 영역에 걸친 단일 모드 특성, 특이한 모드분산 강한 비선형 등의 기존의 광섬유와는 다른 광특성이 보고되고 있으며 테라 헐즈 펄스 도파가 보고되는 등 그 응용 영역을 넓히고 있다. (중략)

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A Study on Properties of Magnetic Field for Development of the Coil Type Magnetometer (코일형 자계 측정기 개발을 위한 자계 특성에 관한 연구)

  • Park, Geon-Ho
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2017.07a
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    • pp.133-134
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    • 2017
  • 전선으로부터 발생되는 저주파 자장을 검출할 수 있고 휴대성 및 가격 경쟁력이 있는 코일형 자계 측정기를 개발하기 위해 본 연구에서 제시된 전선용 자계 검출 센서는 자기 코어 및 코일 권선수 및 길이의 변화에 따른 자계 검출 감도를 분석하여 활선 상태 및 자계의 세기를 확인하여 최적화 구조를 설정하였다.

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Design and Analysis of a Segmented Mode Size Converter with Short Taper Length (?은 테이퍼 길이를 가지는 분리형 모드 크기 변환기의 설계 및 분석)

  • 박보근;정영철
    • Proceedings of the Optical Society of Korea Conference
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    • 2003.07a
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    • pp.208-209
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    • 2003
  • 고밀도 광집적회로의 광도파로는 단일모드 광섬유와 굴절률의 차이 및 코어 크기에 의해 모드 부정합 문제가 존재한다. 본 논문은 이러한 모드 부정합 문제를 해결할 수 있는 모드 크기 변환기를 설계 하고 3-D Beam Propagation Method (BPM)을 이용하여 분석하였다. 모드 크기 변환기술에는 마이크로 렌즈, 테이퍼 광섬유, 렌즈화 광섬유가 사용되고 있으나 이는 패키징 가격이 높으며 광섬유와의 정렬 문제가 존재하므로, 집적된 실리콘 기판위에 제작하는 모드 크기 변환기에 대한 연구가 다각도에서 시도되고 있다. (중략)

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