• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.324-329
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• 2002

In the high-speed/low-power digital filter applications like wireless communication systems, canonical signed digit(CSD) linear phase finite impulse response(FIR) filter structures are widely investigated. In this paper, we propose a high-speed/low-power CSD linear phase FIR filter structure using vertical common sub-expression. In the conventional linear phase CSD filter, horizontal common sub-expressions are utilized due to the inherent horizontal common sub-expression of symmetrical filter coefficients. We use the fact that their MSBs are also equal since adjacent filter coefficients have similar values in the linear phase filter Through the examples, it is shown that our proposed structure is more efficient in case that precision of implementation is lower, and tap length are longer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1970-1982
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• 1993

This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform (VR-FCT), and its VLSI implementation. By mapping the 2-D VR-FCT onto a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently importanted with high concurrency and local communication geometry. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required, which is invitable in the conventional row-column decomposition approach. It has the time complexity of O(N+Nnzp-log2N) for (N*N) 2-D DCT, where Nnzd is the number of non-zero digits in canonic-signed digit(CSD) code, By adopting the CSD arithmetic in circuit desine, the number of addition is reduced by about 30%, as compared to the 2`s complement arithmetic. The computational accuracy analysis for finite wordlength processing is presented. From simulation result, it is estimated that (8*8) 2-D DCT (with Nnzp=4) can be computed in about 0.88 sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.