• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.450-450
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• 2013

플래시 메모리는 소형화가 용이하고, 낮은 구동 전압과 빠른 속도의 소자 장점을 가지기 때문에 휴대용 전자기기에 많이 사용되고 있다. 현재 사용되고 있는 플로팅 게이트를 이용한 플래시 메모리 소자는 비례축소에 의해 발생하는 단 채널 효과, 펀치스루 효과 및 소자 간 커플링 현상과 같은 문제로 소자의 크기를 줄이는데 한계가 있다. 이 문제를 해결하기 위해 FinFET, nanowire FET, 3차원 수직 구조와 같은 구조를 가진 플래시 메모리에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 비례축소의 용이함과 낮은 누설 전류의 장점을 가진 FinFET 구조를 가진 낸드 플래시 메모리의 전기적 특성에 대해 조사하였다. 메모리의 집적도를 높이기 위하여 비대칭 FinFET 구조를 가진 더블 게이트 낸드 플래시 메모리 소자를 제안하였다. 비대칭 FinFET 구조는 더블 게이트를 가진 낸드 플래시에서 각 게이트 간 간섭을 막기 위해 FinFET 구조의 도핑과 위치가 비대칭으로 구성되어 있다. 3차원 TCAD 시뮬레이션툴인 Sentaurus를 사용하여 이 소자의 동작특성을 시뮬레이션하였다. 낸드 플래시 메모리 소자의 게이트 절연 층으로는 high-k 절연 물질을 사용하였고 터널링 산화층의 두께는 두 게이트의 비대칭 구조를 위해 다르게 하였다. 두 게이트의 비대칭 구조를 위해 각 fin은 다른 농도로 인으로 도핑하였다. 각 게이트에 구동전압을 인가하여 멀티비트 소자를 구현하였고 각 구동마다 전류-전압 특성과 전하밀도, 전자의 이동도와 전기적 포텐셜을 계산하였다. 기존의 같은 게이트 크기를 가진 플로팅 게이트 플래시 메모리 소자에 비해 전류-전압곡선에서 subthreshold swing 값이 현저히 줄어들고 동작 상태 전류의 크기가 늘어나며 채널에서의 전자의 밀도와 이동도가 증가하여 소자의 성능이 향상됨을 확인하였다. 또한 양족 게이트의 구조를 비대칭으로 구성하여 멀티비트를 구현하면서 게이트 간 간섭을 최소화하여 각 구동 동작마다 성능차이가 크지 않음을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.105-111
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• 2007

In this paper, we designed and fabricated a 3-dB tandem coupler using air-bridge technology for millimeter-wane monolithic integrated circuits, operating at W-band($75{\sim}110\;GHz$) frequency. Tightly edge-coupled CPW line has low directivity due to different even-mode and odd-mode phase velocity. To overcome this disadvantage, a 3-dB tandem coupler which comprises the two-sectional weakly parallel-coupled lines with equal phase velocity was designed at W-band. The proposed coupler was fabricated using air-bridge technology to monolithically materialize the uniplanar coupler structure instead of conventional multilayer or wire bonded structure. From the measurements, the coupling coefficient of $2.9{\sim}3.6\;dB$ and the good phase difference of $91.2{\pm}2.9^{\circ}$ were obtained in broad frequency range of $75{\sim}100\;GHz$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.153-159
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• 2005

In this paper, we propose All-Optical WDM Buffer System for resolving the contention of Packets in Optical Packet Switching System. The proposed system consists of tunable wavelength converters based on SOA, N×N AWG, and fiber delay lines. This structure can reduce ASE and cross-talk noise because the contending packets are sent and buffered through each different path determined by a wavelength routing. We also performed buffering experiment for two contending WDM optical pulses with each 50ns width, and found that the contending problem is resolved well.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.44-50
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• 2002

A novel technique for minimization of simultaneous switching noise is Presented. Dual Layer Power Line (DLPL) structure i:; newly proposed for a possible silicon realization of a mutual inductor, with which an instant large current in the power line is half-divided flowing through two different, but closely coupled, layers in opposite directions. This mutual inductance between two power layers enables us to significantly reduce the switching noise. SPICE simulations show that with a mutual coupling coefficient higher than 0.8, the switching noise reduces by 63% compared to the previously reported solutions. This DLPL technique can also be applied to PCB artworks.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.5
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• pp.1000-1006
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• 2007

This paper presents a power detector circuit which monitors the transmitting power for the application in CDMA cell phones. The proposed power detector are composed of coupler for coupling output power and detector fur monitoring output power. The designed coupler has low loss characteristic because it adopts the stripline structure which consists of two ground planes at both sides of signal plane. The design frequency is 824-849MHz which is the Tx band fur CDMA mobile terminal, and the coupling factor of the stripline coupler is -20dB. A schottky barrier diode is adopted for detector design because of its high speed operation with minimized loss. The required impedance matching is performed to improve the linearity and sensitivity of output voltage at relatively low detector input level where the nonlinear characteristic of diode exists. The package parasitics as well as intrinsic diode model are considered for simulation of the detector. The predicted performances agree well with the measured results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.36-41
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• 2007

We report the 94 GHz CPW branch-line bandpass filter for planar integrated millimeter-wave circuits. The branch-line coupler operates as a transversal filtering section by connecting the coupling ports to the open load stubs and taking the isolation port as the output node. For design of the 94 GHz branch-line bandpass filter, we built the CPW library and optimized the characteristic impedances and the lengths of the branch-line coupler and the open load stubs. The fabricated 94 GHz bandpass filter exhibits an insertion loss of 2.5 dB with an 11.7 % 3 dB relative bandwidth and the return loss is -18.5 dB at a center frequency of 94 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.547-552
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• 2007

In this paper, the coupled microstrip lines of hairpin type are applied to design a compact microstrip ring hybrid. When the gap decreases, three attenuation poles are created by coupling between the lines. The proposed structure can achieve a significant reduction of size and suppression of the harmonics. And it has the same frequency responses of conventional ring hybrid at 2.55 GHz. The harmonics are suppressed to below -20 dB up to 12 GHz, including the third harmonic. The ring part size of the proposed ring hybrid is reduced to one forth of the conventional ring hybrid. The measured frequency responses agree well with simulated ones.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.3
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• pp.361-366
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• 2012

This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 ${\mu}m$ CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled $g_m$-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.753-759
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• 2014

This paper introduces the reduction design technique of the resonance phenomenon of the inner PCB based on power integrity from the analysis about the inner power supply line generating RLC resonance. With the technique, the resonant frequency resulted from the structural characteristics of the PCB can be analyzed and allows to predict and the capacitor for resonance phenomenon reduction can be decided as a decoupling capacitor. From the simulation result, it was confirmed that the PCB's resonance phenomenon reduction design technique should have the reduction effect in the inner motherboard of the industrial controller. This research will be contributed to the improvement of the safety of a PDN (Power Delivery Network) structure in the layout design technique of the PCB.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.12
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• pp.1209-1218
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• 2016

In order to safely and speedily transport a load such as a large glass plate using four electric cylinders, the synchronous error outside the permitted range should not be continuously generated between the cylinders. In this study, a methodology of synchronous control which can be applied to synchronization of four or more cylinders is developed. The synchronous control system based on the decoupling structure is composed of a reference model, position and synchronous controllers in the respective cylinders. The reference model is used for calculating the decoupled synchronous error and control input for the each cylinder. The position controller of I-PD type is designed in order that the cylinder may follow the reference signal without overshoot and input saturation. And the synchronous controller of lead compensator is designed to achieve stable and accurate synchronization through loop shaping approach. Finally, the simulation results show that the synchronization between the four cylinders can be quickly and stably while each cylinder rod is transferred to the target point under torque disturbance.