• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.10-15
• /
• 2008

In this paper, a new NMOS gate cross-connected current-mirror type bridge rectifier for UHF RFID applications is presented. The DC converting characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit and the gate capacitance reduction technique for reducing the gate leakage current due to the increasing of operating frequency is also proposed theoretically by circuitry method. As the results, the proposed rectifier shows nearly same DC output voltages as the existing NMOS gate cross-connected rectifier, but it shows the gate leakage current reduced to less than 1/4 and the power consumption reduced more than 30% at the load resistor, and it shows more stable DC supply voltages for the valiance of load resistance. In addition, the proposed rectifier shows high enough and well-rectified DC voltages for the frequency range of 13.56MHz HF(for ISO 18000-3), 915MHz UHF(for ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Therefore, the proposed rectifier can be used as a general purpose one to drive RFID transponder chips on various RFID systems which use specified frequencies.

• Applied Chemistry for Engineering
• /
• v.18 no.3
• /
• pp.205-212
• /
• 2007

In this work, polyacrylonitrile (PAN) fiber was prepared by electrospinning methods from dimethyl formamide solutions with various conditions, such as 8~20 kV applied voltage, 5~15 wt% PAN concentration, and 15 cm tip-to-collector distance (TCD). The nanofibers were stabilized by oxidation at $250^{\circ}C$ for 1 h, and then subsequently carbonized at $800{\sim}1000^{\circ}C$ for 1 h. The structured characteristics of the nanofibers before and after carbonization were studied by Fourier transform infrared spectroscopy. The resulting diameter distribution and morphologies of the nanofiber were evaluated by scanning electron microscope analysis. The electrochemical behaviors of the nanofiber were observed by cyclic voltammetry tests. From the results, the diameter of electrospinning nanofibers was predominantly influenced by the concentration of polymer solution and the applied voltage. The average diameter of the fibers was decreased with increasing the polymer concentration up to 10wt%. It was also found that the nanofibers with uniform diameter distribution and fine diameter could be achieved at 15kV input voltage and 15 cm TCD.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.11
• /
• pp.2541-2547
• /
• 2010

In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.569-572
• /
• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.08a
• /
• pp.163-163
• /
• 2010

중적외선 영역 ($3{\sim}5\;{\mu}m$)은 공기 중에 존재하는 이산화탄소나 수증기에 의해 흡수가 일어나지 않기 때문에 군사적으로 중요한 파장 영역이며, 야간에 적을 탐지하는데 응용되고 있다. InSb는 77 K에서 중적외선 파장 흡수에 적합한 밴드갭 에너지 (0.228 eV)를 갖고 있으며, 다른 화합물 반도체와 달리 전하 수송자 이동도 (전자: $10^6\;cm^2/Vs$, 정공: $10^4\;cm^2/Vs$)가 매우 빠르기 때문에 적외선 화상 감지기 재료로 매우 적합하다. 또한 현재 중적외선 영역대에서 널리 사용되는 HgCdTe (MCT)와 대등한 소자 성능을 나타냄과 동시에 낮은 기판 가격, 소자의 제작 용이성 때문에 MCT를 대체할 물질로 주목 받고 있다. 하지만, 기판과 절연막의 계면에 존재하는 결함 때문에 에너지 밴드갭 내에 에너지 준위를 형성하여 높은 누설 전류 특성을 보인다. 따라서 InSb 적외선 소자의 구현을 위하여 고품질의 절연막의 연구가 필수적이라고 할 수 있겠다. 절연막의 특성을 알아보기 위해, n형 InSb 기판에 플라즈마 화학 기상 증착법 (PECVD)을 이용하여 $SiO_2$, $Si_3N_4$를 증착하였으며, 증착 온도를 $120^{\circ}C$에서 $240^{\circ}C$까지 $40^{\circ}C$ 간격으로 변화하여 증착온도가 미치는 영향에 대하여 알아보았다. 절연막과 기판의 계면 특성을 분석하기 위하여 77 K에서 커패시턴스-전압 (C-V) 분석을 하였으며, 계면 트랩 밀도는 Terman method를 이용하여 계산하였다 [1]. $Si_3N_4$를 증착하였을 경우, $120{\sim}240^{\circ}C$의 증착 온도에서 $2.4{\sim}4.9{\times}10^{12}\;cm^{-2}eV^{-1}$의 계면 트랩 밀도를 가졌으며, 증착 온도가 증가할수록 계면 트랩 밀도가 증가하는 경향을 보였다. 또한 모든 증착 온도에서 flat band voltage가 음의 전압으로 이동하였다. $SiO_2$의 경우 $120{\sim}200^{\circ}C$의 증착온도에서 $7.1{\sim}7.3{\times}10^{11}\;cm^{-2}eV^{-1}$의 계면 트랩 밀도 값을 보였으나, $240^{\circ}C$ 이상에서 계면 트랩밀도가 $12{\times}10^{11}\;cm^{-2}eV^{-1}$로 크게 증가하였다. $SiO_2$ 절연막을 사용함으로써, $Si_3N_4$ 대비 약 25% 정도 낮은 계면 트랩 밀도를 얻을 수 있었으며, 모든 증착 온도에서 양의 전압으로 flat band voltage가 이동하였다. 두 절연막에 대한 계면 트랩의 원인을 분석하기 위하여 XPS 측정을 진행하였으며, 깊이에 따른 조성 분석을 하였다. 본 실험에서 최적화된 $SiO_2$ 절연막을 이용하여 InSb 소자의 pn 접합 연구를 진행하였다. Be+ 이온 주입을 진행하고, 급속열처리(RTA) 공정을 통하여 p층을 형성하였다. -0.1 V에서 16 nA의 누설 전류 값을 보였으며, $2.6{\times}10^3\;{\Omega}\;cm^2$의 RoA (zero bias resistance area)를 얻을 수 있었다.

• 한국신재생에너지학회:학술대회논문집
• /
• 2010.11a
• /
• pp.73.2-73.2
• /
• 2010

휴대용 전자기기들의 소비전력 증가에 따라 2차전지에 비해 에너지 밀도가 높은 연료전지를 이용한 충전기의 필요성이 부각되고 있다. 대다수의 충전기는 On-Grid 방식으로 벅타입 컨버터를 이용한 감압 방식이었으나, 연료전지를 이용할 경우 승압식 컨버터를 통한 배터리의 충전이 요구된다. 또한 배터리는 일반 저항부하와 달리 큰 커패시턴스 성분을 가지고 있기 때문에 컨버터의 출력단에 인덕터가 없는 경우 큰 출력 리플전류를 유도하게 되어 시스템의 효율과 배터리의 수명에 좋지 않은 영향을 끼치게 된다. 또한 이를 해결하기 위해 절연형 감압 컨버터를 사용하는 경우 변압기 사용에 의한 부피 증가와 부가 소자의 사용에 따른 가격 상승을 피하기 어렵다. Cuk 컨버터는 주스위치의 ON/OFF 동작에 관계없이 출력으로 에너지가 항상 전달되며, 이상적으로 리플이 거의 존재하지 않아 충전용으로 적합하다. 또한, 승압 및 감압이 자유롭기 때문에 배터리의 정격전압에 상관없는 범용 충전기의 설계도 가능하다. 따라서 본 논문에서는 Cuk 컨버터를 이용하여 배터리 충전기를 설계하고, 그의 상태공간 모델링, 주파수 특성 해석 및 제어기 설계에 대해 기술한다. 제안된 제어 방식은 소형 연료전지 스택을 이용하여 실제 배터리를 대상으로 한 정전류 및 정전압 제어를 실행하여 그 성능 및 안정성을 검증한다.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.33 no.4
• /
• pp.125-131
• /
• 2023

Ga₂O₃ thin films were deposited on Ti substrates using metal organic chemical vapor deposition (MOCVD) at temperatures ranging from 350 to 500℃. Lower deposition temperatures were chosen to minimize thermal deformation of the Ti substrate and its impact on the Ga₂O₃ film. Film surfaces tended to become rough at temperatures below 500℃ due to three-dimensional growth, but the film formed at 500℃ had the most uniform surface. All deposited films were amorphous in structure. Vertical Schottky diodes were fabricated and I-V and C-V measurements were performed. I-V measurements showed higher operating voltages compared to a typical SBD for films grown at different temperatures. The sample grown at 500℃, which had the most uniform surface, exhibited the lowest operating voltage. Higher growth temperatures resulted in higher capacitance values according to C-V measurements.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.4
• /
• pp.14-23
• /
• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.47 no.2
• /
• pp.35-42
• /
• 2010

In this study, crosstalk between dominant interconnect pairs in an A/D converter circuit is analyzed in frequency domain and effects of termination conditions on crosstalk are described, based on the practical circuit conditions. An A/D converter circuit is a mixed circuit where both clean and noisy signals coexist such that the circuit probably suffers from distortion by crosstalk. An analog input signal and the reference voltage signal, which dominate the overall conversion performance of the A/D converter circuit, are ready to be distorted by crosstalk and include specific termination conditions, such as non-matching and capacitive termination, respectively. Thus, this study presents the model of crosstalk considering impedance mismatch at both ends and analyzes effects of the practical termination conditions in the analog input and the reference voltage interconnects on crosstalk. A typical circuit configuration of the two interconnects is described and crosstalk including near-end and far-end termination impedances is modeled. Effects of the near-end impedance mismatch in the analog input interconnect and the far-end capacitive termination in the reference voltage interconnect are estimated in the frequency domain by using the model of crosstalk and experiments are performed to confirm the estimated results. Microstrip lines are used as interconnects, involving the increase of loss in high frequencies.

• Korean Journal of Materials Research
• /
• v.11 no.4
• /
• pp.247-250
• /
• 2001

We have fabricated and evaluated a new Si pin photodiode for red light detection with the web patterned $p^{+}$ -shallow diffused region in the light absorbing area. From the measurements of electro-optical characteristics under the bias of -5V, the junction capacitance of 4pF and the dark current of 235pA were obtained. When the 1.6㎼ optical power with peak wavelength of 670nm was incident on the device, the optical signal current of 0.48$\mu\textrm{A}$ and the responsivity of 0.30A/W were obtained. The fabricated device showed the improved sensitivity compared to the conventional circular type device and the maximum spectral response in a spectrum of 670~700nm. The web-patterned Si photodiode can be expected to have the good discrimination characteristics between digital signals in the application of red light optics.