• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4126-4130
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• 2012

In this paper, we proposed planar spiral inductors based on AC coupling for high-frequency wireless signal transmission. Design and characteristics of various structures of the inductor were analyzed. Capacitance between the inductors can be reduced by positioning two thin-film inductors in parallel. So two structures were proposed. First structure is inter-diagonal structure. This structure was made not to overlap the wire part of the paralleled two inductors. Second structure is On-chip type structure that the two thin-film inductors were in parallel but located on diagonal line not to face each other. The resonance in this structure was reduced from twice to once by increasing horizontal distance between the two thin-film inductors, because the capacitance effect between the two thin-film inductors decreases when the distance between the two inductors increases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.10-21
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• 2006

We have studied the characteristics of oxide VCSELS when their off-current and on-current are kept small in order to find out the possibility of low current operation. A large signal equivalent circuit model has been used. By comparing measured data and simulation results, the parameters of the large signal models are obtained including the capacitances. Using the large signal model, we have investigated the effects of capacitance and on/off currents upon the turn-on/turn-off characteristics and eye diagram. According to the experiment and simulation, the depletion capacitance, which has been neglected, is found to have significant influence on the him-on delay and eye-diagram. Therefore, for high speed and low current operation, the reduction of the depletion capacitance is essential.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1591-1592
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• 2006

이동 및 정보통신 시스템이 소형화 및 고성능화됨에 따라 System OR Package (SOP) 기술의 연구개발이 주목을 받고 있다. 저가형 SOP를 위하여 가장 많은 연구가 다층인쇄회로 기판에 수동소자 및 전송선로를 내장시키는 것이다. 본 논문에서는, 8층 KB 기판에 Meander line과 Radial/T Stub 패턴을 Advanced Design System(ADS) simulation을 이용하여 설계 및 제작하고 분석함으로써 정확한 SOP 디자인 및 설계 방향을 제시하고자 한다. 설계변수-패턴의 length, width, spacing, 각도와 공정변수-1층/3층, 기판 재질(prepreg(PP)과 resin coated copper(RCC))을 두어 제작하여 그 특성을 비교하였다. Meander Line는 PP보다 RCC에서의 인덕턴스가 크고 높은 자가 공진주파수를 가졌고, 3층보다 1층에서의 인덕턴스가 안정적이었다. Radial/T Stub는 PP보다 RCC에서의 커패시턴스가 작으나, 높은 자가 공진 주파수로 커패시턴스가 안정적이었다. Meander Line은 RCC, 병렬 전송선로 간격-400um, 병렬 전송선로 길이-500um, 1층 설계 시, 인덕턴스-1.60nH, 자가 공진주파수-9.21GHz 특성이 가장 우수하고, Radial Stub는 RCC, $60^{\circ}$, 1층 설계 시, 커패시턴스-0.62pF, 자가 공진주파수-9.06GHz의 특성이 나타났고, T Stub는 RCC, Stub 길이-600um, Stub 너비-150um, 1층 설계 시, 커패시턴스 -0.38pF, 자가 공진주파수-10GHz이상으로 우수한 특성을 나타냈다.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.118-125
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• 1999

A capacitance method to extract the metallurgical channel length of LDD MOSFET's, which is defined by the length between the metallurgical junction of substrate and source/drain under the gate, is presented. The gate capacitances of the finger type and plate type LDD MOSFET gate test patterns with same total gate area are measured. The gate bias of each pattern is changed, and the capacitances are measured with source, drain, and substrate bias grounded. The differences between two test pattern's capacitance data are plotted. The metallurgical channel length is extracted from the peak data at a maximum point using a simple formula. The numerical simulation using two-dimensional device simulator is performed to verify the proposed method.

• Journal of IKEEE
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• v.22 no.3
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• pp.780-785
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• 2018

In this work, We investigated the frequency-dependent capacitance tunability of a metal-ferroelectric-metal variable capacitor fabricated using ALD $HfO_2$ ferroelectric material. The capacitance of the MFM capacitor could be tuned as a function of the bias voltage, up to the microwave frequency range. We observed a capacitance tuning range of ~3 % up to 2.5 GHz, proving the feasibility of the use of ALD $HfO_2$ in the microwave frequency band.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.5
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• pp.387-393
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• 2010

This paper proposes a correction method of capacitance estimation considering the temperature effect for the DC-link capacitor banks in three-phase AC/DC/AC PWM converters. At first, operating temperature of the capacitors is detected and capacitance variation is corrected due to the temperature effect. Thermisters are used for sensing the temperature and voltage variation across the thermister is exploited to identify the capacitance change. The validity of the proposed method has been verified by experimental results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.5
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• pp.486-487
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• 1997

This paper presents the pure capacitive lumped element equivalent circuits for several coplanar waveguide(CPW) discontinuities such as an open-end, an open-end with connected ground planes, a gap and an open-end CPW stub and gives their capacitive element values as a function of physical dimensions of the discontinuity and the frequency for a specific substrate. The capacitive element values are determined from the scattering parameters which are obtained using the finite-difference time-domain(FDTD) method. For an open-end, an open-end with connected ground planes and a gap, the numerical results of the FDTD are compared with the quasi-static results which are calculated using the three- dimensional finite difference method(3D-FDM).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.7
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• pp.64-72
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• 1992

The capacitance for three-dimensional (3D) VLSI interconnection line is calculated. Capacitance is obtained by solving integral equation that is the product of Green's function and surface charge density. Surface charge density is assumed that constant in each subarea, and subarea is devided by rectangular size in interconnetion surfaces. Up to date, so this integral method using Green's function is calculated by Fourier integral transformation, that it cannot help making an error. In this paper, it is proposed to use direct integration instead of Fourier integral method. And we proved accuracy of this paper in comparision with conventional results.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.82-88
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• 2014

An available capacitance increasing phase-locked loop(PLL) with two voltage controlled oscillator gains has been proposed. In this paper, the available capacitance of loop filter is increased by using two positive/negative gains of voltage controlled oscillator (VCO). It results in 1/10 reduction in the size of loop filter capacitor. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and a locking time of conventional PLL.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.4
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• pp.399-402
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• 2016

We propose a thin electromagnetic wave absorber using varactor diodes combined with intentionally introduced multiple slits, which enables continuous sweep of an absorption frequency band throughout relatively wide frequencies. The absorption frequency range of conventional electrically tunable absorbers has been restricted by high capacitance of varactor diodes. In order to overcome the problem, we introduce parasitic capacitance and connect them with varactors in series, which reduces the total capacitance dramatically. As a result, we can raise the operating absorption frequency up to the X-band region. Moreover, we can also control the operating frequencies by modifying the number of slits with little change in an entire frequency sweep range. Good agreement between simulated and measured results show the validity of our proposal.