• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.652-653
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• 2014

This paper present a method of GRM constant generation using cell [fi] which is generated over karnaugh map. The proposed method is as following. First od all, we select the arbitrary cell over karnaugh map. Next we arithmetic operate the selected cell with single variable transformation matrix, and mapping into karnaugh map its result. Although we discuss the new GRM generation method applied to polarity circulation.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1997.11a
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• pp.315-321
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• 1997

본 논문에서는 임의의 부울함수(Boolean function)에 대한 진리표나 출력 시퀀스로부터 논리곱의 배타적 합(exclusive-or sum of products; ESOP)형의 부울함수를 구성하는 알고리듬을 제안한다. 기존에 알려진 카르노맵이나 Quine HcClusky법에 의하여 구해지는 부울함수는 논리곱의 합(sum of product; SOP) 형으로 주어지며 이들 수식은 부정(NOT)논리를 포함하는 경우가 있다. 제안된 알고리듬에 의하여 구해지는 부울함수는 구조적인 등가성을 판별하는데 편리하므로 해쉬함수용 부울함수의 개발에 이용될 수 있다.

• Journal of Internet Computing and Services
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• v.16 no.3
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• pp.33-41
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• 2015

In this paper, the simplification procedure of Karnaugh Map, which is essential to design digital logic circuits, was implemented as web-based educational Java applets. The learners will be able to experience interesting learning process by executing the proposed Java applets. In addition, since the proposed Java applets were designed to contain educational technologies by step-by-step procedure, the maximization of learning efficiency can be obtained. The learners can make virtual experiments on the simplification of digital logic circuits by clicking on some buttons or filling out some text fields. Furthermore, the Boolean expression and its schematic diagram occurred in the simplification process will be displayed on the separate frame so that the learners can learn effectively. The schematic diagram enables them to check out if the logic circuit is correctly connected or not. Finally, since the simplification algorithm used in the proposed Java applet is based on the modified Quine-McCluskey minimization technique, the proposed Java applets will show more encouraging result in view of learning efficiency if it is used as assistants of the on-campus offline class.

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.83-92
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• 2012

This paper suggests an improved method of grouping minterms based on the Decimal-Valued Matrix (DVM) method. The DVM is a novel approach to Boolean logic minimization method which was recently developed by this author. Using the minterm-based matrix layout, the method captures binary number based minterm differences in decimal number form. As a result, combinable minterms can be visually identified. Furthermore, they can be systematically processed in finding a minimized Boolean expression. Although this new matrix based approach is visual-based, the suggested method in symmetric grouping cell values can become rather messy in some cases. To alleviate this problem, the enhanced DVM method that is based on multi-level groupings of combinable minterms is presented in this paper. Overall, since the method described here provides a concise visualization of minterm groupings, it facilitates a user with more options to explore different combinable minterm groups for a given Boolean logic minimization problem.

• The Journal of Korean Association of Computer Education
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• v.10 no.4
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• pp.17-25
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• 2007

In this paper, the simplification procedure of Karnaugh Map, which is essential to design digital logic circuits, was implemented as a web-based educational tool by Java applet. The learners can make virtual experiments on the simplification of the digital logic circuit by clicking on some buttons or filling out some text fields. The proposed simplification procedure was implemented as a Java applet which is based on the Modified Quine-McCluskey algorithm. Thus, the implemented Java applet will enable the learners to enhance the learning efficiency as a auxiliary educational tool.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.95-102
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• 2015

This paper proposes a simple algorithm for circuit minimization. There are currently two effective heuristics for circuit minimization, namely manual Karnaugh maps and computable Quine-McCluskey algorithm. The latter, however, has a major defect: the runtime and memory required grow $3^n/n$ times for every increase in the number of variables n. The proposed algorithm, however, extracts the prime implicants (PI) that cover minterms of a given Boolean function by deriving an implicants table based on frequency. From a set of the extracted prime implicants, the algorithm then eliminates redundant PIs again based on frequency. The proposed algorithm is therefore capable of minimizing circuits polynomial time when faced with an increase in n. When applied to various 3-variable and 4-variable cases, it has proved to swiftly and accurately obtain the optimal solutions.