• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.66-74
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• 1995

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at ＋5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.4
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• pp.1789-1796
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• 2012

In this paper, a new high-efficiency CMOS bridge rectifier for driving RFID tag chips is designed and analyzed. The input stage of the proposed rectifier is designed as a cascade structure connected with two NMOSs for reducing the gate capacitance by circuitry method, which is the main path of the leakage current that is increased when the operating frequency is increased. This gate capacitance reduction technique using the cascade input stage for reducing the gate leakage current is presented theoretically. The output characteristics of the proposed rectifier are derived analytically using its high frequency small-signal equivalent circuit. For the general load resistance of $50K{\Omega}$, the proposed rectifier shows better power conversion efficiencies of 28.9% for 915MHz UHF (for ISO 18000 -6) and 15.3% for 2.45GHz microwave (for ISO 18000-4) than those of 26.3% and 26.8% for 915MHz, and 13.2% and 12.6% for 2.45GHz of compared other two existing rectifiers. Therefore, the proposed rectifier may be used as a general purpose rectifier to drive tag chips for various RFID systems.

• Korean Journal of Materials Research
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• v.5 no.8
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• pp.929-935
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• 1995

In order to develop COG (Chip On Glass) technology for LCD module interconnecting the driver IC to Al pad electrode on the glass substrate, Anisotropic Conductive Adhesive(ACA) process, the most promising one among COG technologies, was investigated. ACA process was carried out by two steps, dispensing of ACA resin in the bonding area and curing by W radiation. Load on the chip was ranged from 2.0 to 15kg and the chip was heated at about 12$0^{\circ}C$. In resin, the density of conductive particles coated with Au or Ni at the surface were 500, 1000, 2000 and 4000 particles/$\textrm{mm}^2$, and the diameter of particles were 5, 7 and 12${\mu}{\textrm}{m}$. As a result of the experiments, ACA process using ACA particle of diameter and density of 5${\mu}{\textrm}{m}$ and 4000 particles/$\textrm{mm}^2$ respectively shows optimum characteristic with the stabilzed bonding properties and contact resistance.

• Journal of Sensor Science and Technology
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• v.12 no.2
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• pp.57-65
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• 2003

When a vision chip for edge detection using CMOS process is designed, there is a necessity to implement local light adaptive-function for detecting distinctive features of an image at a wide range of light intensities. Local light adaptation is to achive the almost same output level by changing the size of receptive-fields of the local horizontal cell layers according to input light intensities, based on the lateral inhibitive-function of the horizontal cell. Thus, the almost same output level can be obtained whether input light intensities are much or less larger than background. In this paper, the horizontal cells using a resistive network which consists of p-MOSFETs were modeled and analyzed, and the local light adaptive-mechanism of the designed vision chip using the resistive network was verified.

• Korean Journal of Materials Research
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• v.9 no.11
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• pp.1095-1101
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• 1999

Electroless Ni plating is applied to form bumps and UBM layer for flip chip interconnection. Characteristics of electroless Ni are also investigated. Zincate pretreatment is analyzed and plated layer characteristics are investigated according to variables like temperature, pH and heat treatment. Based on these observations, characteristics dependence to each variables and optimum electroless Ni plating conditions for flip-chip interconnection are suggested. Electroless Ni has 10wt% P, $60\mu\Omega$-cm resistivity, 500HV hardness and amorphous structure. It changes crystallized structure and hardness increases after heat treatment After interconnection of electroless Ni bumps by ACF flip chip method, we show their advantages and possibility in microelectronic package applications.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.95-100
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• 2010

LED (Light Emitting Diode) is 85% of the applied energy is converted into heat that is already well known. Lately, LED chips increasing the capacity as result delivered to increase the heat of the LED products and module that directly related to life span and degradation. Thus, in industry the high-power LED chip to control the heat generated during the course of the study and the existing aluminum, copper adhesives, and uses MLC (Metal clad laminate) structures using low-cost FR4 and copper CCL (Copper Clad Laminate) to reduce costs by changing to a study being carried out. In this study, using low-cost CCL Class, mounted 1W LED chip to analyze changes in the thermal resistance. In addition, heat dissipation in the CCL to facilitate a variety of thermal via design outside of the heat generated by the LED chip to control and facilitate the optimal structure of the heat dissipation is suggested.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.1-6
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• 2014

Flip chip bonded LED packages possess lower thermal resistance than wire bonded LED packages because of short thermal path. In this study, thermal and bonding properties of flip chip bonded high brightness LED were evaluated for Au-Sn thermo-compression bonded LEDs and Sn-Ag-Cu reflow bonded LEDs. For the Au-Sn thermo-compression bonding, bonding pressure and bonding temperature were 50 N and 300oC, respectively. For the SAC solder reflow bonding, peak temperature was $255^{\circ}C$ for 30 sec. The shear strength of the Au-Sn thermo-compression joint was $3508.5gf/mm^2$ and that of the SAC reflow joint was 5798.5 gf/mm. After the shear test, the fracture occurred at the isolation layer in the LED chip for both Au-Sn and SAC joints. Thermal resistance of Au-Sn sample was lower than that of SAC bonded sample due to the void formation in the SAC solder.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.6
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• pp.673-680
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• 2017

Research and commercialization of wood chips-urethane resin mixtures as paving materials for park trails and tourist attractions are underway. The aim of this study was to expand the use of such paving materials to the playgrounds, where vigorous physical movements occur frequently. For this purpose, the physical properties and safety of the paving material, in which some or all of the wood chips(passing through a 10mm sieve and remaining in a 3mm sieve) were replaced with sawdust, were studied experimentally. Strength, elastic modulus, slip resistance, shock absorption and heavy metal content tests were carried out by varying the mixing ratio of urethane resin, sawdust and wood chip. As a result, in the case of wood chip-resin mixtures with mass ratios of the resin to total mass of sawdust and wood chips of 1.0 and 1.2 and having a ratio of sawdust mass to total mass of sawdust and wood chips of 0-0.4, it was found that the properties satisfied KS F 3888-2. On the other hand, in case of using sawdust only as a woody material, the shock absorbability was below standard, and the mass ratio of resin to sawdust required 1.2 or more to ensure the specified tensile strength.

• Journal of the Korean Wood Science and Technology
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• v.16 no.2
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• pp.1-41
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• 1988

For the purpose of utilizing the sawdust having poor combining properties as board raw material and resulting in dimensional instability of board, polypropylene chip (abbreviated below as PP chip) or oriented PP thread was combined with sawdust particle from white meranti(Shorea sp.). The PP chip was prepared from PP thread in length of 0.25, 0.5, 1.0 and 1.5 cm for conventional blending application. Thereafter, the PP chip cut as above was combined with the sawdust particle by 3, 6, 9, 12 and 15% on the weight basis of board. Oriented PP threads were aligned with spacing of 0.5, 1.0 and 1.5cm along transverse direction of board. The physical and mechanical properties on one, two and three layer boards manufactured with the above combining conditions were investigated. The conclusions obtained at this study were summarized as follows: 1. In thickness swelling, all one layer boards combined with PP chips showed lower values than control sawdustboard, and gradually clear decreasing tendendy with the increase of PP chip composition. Two layer board showed higher swelling value than one layer board, but the majority of boards lower values than control sawdustboard. All three layer boards showed lower swelling values than control sawdustboard. 2. In the PP chip and oriented thread combining board, the swelling values of boards combining 0.5cm spacing oriented thread with 1.0 or 1.5cm long PP chip in 12 and 15% by board weight were much lower than the lowest of one or three layer. 3. In specific gravity of 0.51, modulus of rupture of one layer board combined with 3% PP chip showed higher value than control sawdustboard. However, moduli of rupture of the boards with every PP chip composition did not exceed 80kgf/cm2, the low limit value of type 100 board, Korean Industrial Standard KS F 3104 Particleboards. Moduli of rupture of 6%, 1.5cm-long and 3% PP chip combined boards in specific gravity of 0.63 as well as PP chip combined board in specific gravity of 0.72 exceeded 80kgf/$cm^2$ on KS F 3104. Two layer boards combined with every PI' chip composition showed lower values than control sawdustboard and one layer board. Three layer boards combined with.1.5cm long PP chip in 3, 6 and 9% combination level showed higher values than control sawdustboard, and exceeded 80kgf/$cm^2$ on KS F 3104. 4. In modulus of rupture of PP thread oriented sawdustboard, 0.5cm spacing oriented board showed the highest value, and 1.0 and 1.5cm spacing oriented boards lower values than the 0.5cm. However, all PP thread oriented sawdustboards showed higher values than control saw-dustboard. 5. Moduli of rupture in the majority of PP chip and oriented thread combining boards were higher than 80kgf/$cm^2$ on KS F 3104. Moduli of rupture in the boards combining longer PP chip with narrower 0.5cm spacing oriented thread showed high values. In accordance with the spacing increase of oriented thread, moduli of rupture in the PP chip and oriented thread combining boards showed increasing tendency compared with oriented sawdustboard. 6. Moduli of elasticity in one, two and three layer boards were lower than those of control sawdustboard, however, moduli of elasticity of oriented sawdustboards with 0.5, 1.0 and 1.5cm spacing increased 20, 18 and 10% compared with control sawdustboard, respectively. 7. Moduli of elasticity in the majority of PP chip and oriented thread combining boards in 0.5, 1.0 and 1.5cm oriented spacing showed much higher values than control sawdustboard. On the whole, moduli of elasticity in the oriented boards combined with 9% or less combination level and 0.5cm or more length of PP chip showed higher values than oriented sawdustboard. The increasing effect on modulus of elasticity was shown by the PP chip composition in oriented board with narrow spacing. 8. Internal bond strengths of all one layer PP chip combined boards showed lower values than control sawdust board, however, the PP chip combined boards in specific gravity of 0.63 and 0.72 exceeded 1.5kgf/$cm^2$, the low limit value of type 100 board and 3kgf/$cm^2$, type 200 board on KS F 3104, respectively. And also most of all two, three layer-and oriented boards exceeded 3kgf/$cm^2$ on KS F. 9. In general, screw holding strength of one layer board combined with PP chip showed lower value than control sawdustboard, however, that of two or three layer board combined with PP chip did no decreased tendency, and even screw holding strength with the increase of PP chip composition. In the PP chip and oriented PP thread combining boards, most of the boards showed higher values than control sawdustboard in 9% or less PP chip composition.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.376-383
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• 2008

Generally a return current plane(RCP) of high speed digital and analog part is partitioned. This is achieved in order to decrease the noise interference between subsystem in PCBs(Printed Circuit Boards). However, when the connected signal line exists between each subsystem, this partition will cause unwanted effects. In a EMI(Electromagnetic Interference) point of view, the partition of the return current plane becomes a primary factor to increase the radiated emission. Component bridge(CB) is used for the way of maintaining radiated emission, still specific user's guide doesn't give sufficient principle. In a view point of EMI, design principle of multi-CB using method will be analyzed by measurement. And design principle of noise mitigation will be provided. Generally interval of multi-CB is ${\lambda}/20$ ferrite bead. In this study, When multi-CB connection is applied, design principle of ferrite bead and chip resistor is proved by measurement. Multi-connected chip resistance$(0{\Omega})$ is proved to be more effective design method in the point of EMI.