• Korean Journal of Metals and Materials
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• v.46 no.9
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• pp.585-592
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• 2008

Flip-chip bonding using Cu-Sn mushroom bumps composed of Cu pillar and Sn cap was accomplished, and the contact resistance and the thermal cycling reliability of the Cu-Sn mushroom bump joints were compared with those of the Sn planar bump joints. With flip-chip process at a same bonding stress, both the Cu-Sn mushroom bump joints and the Sn planar bump joints exhibited an almost identical average contact resistance. With increasing a bonding stress from 32 MPa to 44MPa, the average contact resistances of the Cu-Sn mushroom bump joints and the Sn planar bump joints became reduced from $30m{\Omega}/bump$ to $25m{\Omega}/bump$ due to heavier plastic deformation of the bumps. The Cu-Sn mushroom bump joints exhibited a superior thermal cycling reliability to that of the Sn planar bump joints at a bonding stress of 32 MPa. While the contact resistance characteristics of the Cu-Sn mushroom bump joints were not deteriorated even after 1000 thermal cycles ranging between $-40^{\circ}C$ and $80^{\circ}C$, the contact resistance of the Sn planar bump joints substantially increased with thermal cycling.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1350-1359
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• 2008

This paper presents a wideband doubly balanced resistive mixer fabricated using $0.5{\mu}m$ GaAs p-HEMT process. Three baluns are employed in the mixer. LO and RF baluns operating over an 8 to 20 GHz range were implemented with Marchand baluns. In order to reduce chip size, the Marchand baluns were realized by the meandering multicoupled line and inductor lines were inserted to compensate for the meandering effect. IF balun was implemented through a DC-coupled differential amplifier. The size of IF balun is $0.3{\times}0.5\;mm^2$ and the measured amplitude and phase unbalances were less than 1 dB and $5^{\circ}$, respectively from DC to 7 GHz. The mixer is $1.7{\times}1.8\;mm^2$ in size, has a conversion loss of 5 to 11 dB, and an output third order intercept(OIP3) of +10 to +15 dBm at 16 dBm LO power for the operating bandwidth.

• Horticultural Science & Technology
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• v.34 no.1
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• pp.102-111
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• 2016

The goal of this study was to characterize the BrDSR (Drought Stress Resistance in B. rapa) gene and to identify the expression network of drought-inducible genes in Chinese cabbage under drought stress. Agrobacterium-mediated transformation was conducted using a B. rapa inbred line ('CT001') and the pSL100 vector containing the BrDSR full length CDS (438 bp open reading frame). Four transgenic plants were selected by PCR and the expression level of BrDSR was approximately 1.9-3.4-fold greater than that in the wild-type control under drought stress. Phenotypic characteristics showed that BrDSR over-expressing plants were resistant to drought stress and showed normal growth habit. To construct a co-expression network of drought-responsive genes, B. rapa 135K cDNA microarray data was analyzed to identify genes associated with BrDSR. BrDSR was directly linked to DARK INDUCIBLE 2 (DIN2, AT3G60140) and AUTOPHAGY 8H (ATG8H, AT3G06420) previously reported to be leaf senescence and autophagy-related genes in plants. Taken together, the results of this study indicated that BrDSR plays a significant role in enhancement of tolerance to drought conditions.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.4
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• pp.338-347
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• 2021

In this paper, the beta-ray sensor circuit used in the true random number generator was designed using DB HiTek's 0.18㎛ CMOS process. The CSA circuit proposed a circuit having a function of selecting a PMOS feedback resistor and an NMOS feedback resistor, and a function of selecting a feedback capacitor of 50fF and 100fF. And for the pulse shaper circuit, a CR-RC2 pulse shaper circuit using a non-inverting amplifier was used. Since the OPAMP circuit used in this paper uses single power instead of dual power, we proposed a circuit in which the resistor of the CR circuit and one node of the capacitor of the RC circuit are connected to VCOM instead of GND. And since the output signal of the pulse shaper does not increase monotonically, even if the output signal of the comparator circuit generates multiple consecutive pulses, the monostable multivibrator circuit is used to prevent signal distortion. In addition, the CSA input terminal, VIN, and the beta-ray sensor output terminal are placed on the top and bottom of the silicon chip to reduce capacitive coupling noise between PCB traces.

• Geotechnical Engineering
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• v.7 no.3
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• pp.51-64
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• 1991

The reliable estimation of pile bearing capacity is essential for the improvement of the re- liability and the cost-effectiveness of the design. There have been numerous pile bearing capacity prediction methods proposed up to now, however, execpt for the estimation made from the result of the pile loading test, not one method is appropriate for the reliable prediction. Due to the considerable time and expenses required to carry out the pile loading test, the test has seldom been utilized. The development of Simple Pile Loading Test(SPLT) which utilizes the pile skin friction as the required reaction force to cause the pile tip settlement, provides a solution to perform more pile loading tests and consequently a more economical pile design is possible. The separate measurement of skin friction and tip resistance during the course of performing SPLT provides a better understanding of the pile behavior than the result of the conventional pile loading test where only the total resistance is measured. On the other hand, there are some points to be clarified in order to apply the test results of SPLT to practical problem. They are the direction of the applied load to mobilize the skin friction and the use of reduced sized sliding core. In this research, both the SPLT and the conventional pile loading test on 406mm diameter steel pipe pile have been performed. From the result, it would be safe to use the measured SPLT skin friction value directly in the design, since the value is somewhat lower than the value measured in the conventional test. It is further assumed that the tip resistance value of the reduced sized sliding core should properly be analysed by taking the incluonce of scale effect into consideration.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.53-60
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• 2004

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

• Journal of the Korean Vacuum Society
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• v.21 no.3
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• pp.164-170
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• 2012

The dependance of degradation on the blue-peak wavelength is investigated with the blue light-emitting diode (LED) of InGaN/GaN with respect to the optical and the electrical characteristics of the devices. The LED devices emitting the blue-peak wavelength ranging from 437 nm to 452 nm is prepared to be stressed for a long aging time with three different currents of 60 mA, 75 mA and 90 mA, respectively. The degradation of optical intensity is observed with and without phosphor in the devices. The device without phosphor has been degraded significantly as the wavelength of blue-peak is decreased while the optical intensity of LED device with phosphor become less sensitive than that of device without phosphor. The electrical property does not depend on the emission peak wavelength. However, the series-resistance of LED device is slowly increased as the aging time is increased. The deformation of device is observed severely the short wavelength of blue-peak even with the same current since the short wavelength is absorbed substantially at the materials of device during the aging time. Consequently, in order to enhance the lifetime of LED devices, it is important to understand the optical degradation property of the materials against the specific wavelengths emitted from the blue chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.71-79
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• 2010

This paper presents a design of a LLC resonant controller IC. LLC resonant controller IC controls the voltage of the 2nd side by adjusting frequency the input frequency of the external resonant circuit. The clock generator is integrated to provide the pulse to the resonant circuit and its frequency is controlled by the external resistor. Also, the frequency of the VCO is adjusted by the feedback voltage. The protection circuits such as UVLO(Under Voltage Lock Out), brown out, fault detector are implemented for the reliable and stable operation. The HVG, and LVG drivers can provide the high current and voltage to the IGBT. The designed LLC resonant controller IC is fabricated with the 0.35 um 2P3M BCD process. The overall die size is $1400um{\times}1450um$, and supply voltage is 5V, 15V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.