• Annual Conference on Human and Language Technology
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• 한국정보과학회언어공학연구회 2022년도 제34회 한글 및 한국어 정보처리 학술대회
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• pp.553-558
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• 2022

최근, 구어체 데이터에 대한 자연어처리 응용 기술이 늘어나고 있다. 구어체 문장은 소통 방식 등의 형태로 인해 정제되지 않은 형태로써, 필연적으로 띄어쓰기, 문장 왜곡 등의 다양한 문법적 오류를 포함한다. 자동 문법 교정기는 이러한 구어체 데이터의 전처리 및 일차적 정제 도구로써 활용된다. 사전학습된 트랜스포머 기반 문장 생성 연구가 활발해지며, 이를 활용한 자동 문법 교정기 역시 연구되고 있다. 트랜스포머 기반 문장 교정 시, 교정의 필요 유무를 잘못 판단하여, 오류가 생기게 된다. 이러한 오류는 대체로 문맥에 혼동을 주는 단어의 등장으로 인해 발생한다. 본 논문은 트랜스포머 기반 문법 교정기의 오류를 보강하기 위한 방식으로써, 필요하지 않은 형태소인 고유명사를 마스킹한 입력 및 출력 문장틀 형태를 제안하며, 이러한 문장틀에 대해 고유명사를 복원한 경우 성능이 증강됨을 보인다.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제39A권5호
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• pp.258-270
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• 2014

In this paper, we investigate channel capacity of two kinds of uplink OFDMA (Orthogonal Frequency Division Multiple Access) schemes, i.e. ZCZ (Zero Correlation Zone) code time-spread OFDMA and sparse SC-FDMA (Single Carrier Frequency Division Mmultiple Access) robust to access timing offset (TO) among multiple users. In order to reflect the practical condition, we consider not only access TO among multiple users but also peak to average power ratio (PAPR) which is one of hot issues of uplink OFDMA. In the case with access TO among multiple users, the amplified signal of users by power control might affect a severe interference to signals of other users. Meanwhile, amplified signal by considering distance between user and base station might be distorted due to the limit of amplifier and thus the performance might degrade. In order to achieve the maximum channel capacity, we investigate the combinations of transmit power so called ASF (adaptive scaling factor) by numerical simulations. We check that the channel capacity of the case with ASF increases compared to the case with considering only distance i.e. ASF=1. From the simulation results, In the case of high signal to noise ratio (SNR), ZCZ code time-spread OFDMA achieves higher channel capacity compared to sparse block SC-FDMA. On the other hand, in the case of low SNR, the sparse block SC-FDMA achieves better performance compared to ZCZ time-spread OFDMA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제17권6호
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• pp.519-528
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• 2006

This thesis is regarding of fabricating wibro PAM. First of all, we need to set specification based on link budget for wibro communication circumstance in order to develop PAM, then we decided specification concerning of wibro PAM by considering TTAS_Ko_06_0082R1 which is standarded in Korea, and IEEE Std. 802. 16d/e which is international standard. We selected the Doherty structure to increase efficiency, and pre-distorter structure to increase linearity. The fabricated PAM has not only a result of $26.5dB{\pm}1.0dB$ gain characteristics and maximum of -14 dB return loss characteristics in full frequency bands and full output ranges, but also a result of 37 dBc at 4 tone IMD characteristics which is improved result of 843 and a result of 31 dBc spurious characteristics which is improved result of 5 dB at 4.77 MHz offset point in status of having 27 % efficiency in the 26 dBm high power amplifier output signal. We confirmed the suggested structure is better than others by comparing with normal structure, balanced structure and Doherty structure without predistorter.

• Journal of IKEEE
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• 제2권1호
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• pp.1-14
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• 1998

In this paper, Antenna, LNA, Mixer, VCO, and Modulation/Demodulation in Baseband processor which are the RF main components in Wireless LAN system for ultra high-speed communications network are studied. Antenna bandwidth and selective fading due to multipath can be major obstacles in high speed digital communications. To solve this problem, wide band MSA which has loop-structure magnetic antenna characteristics is designed. Distributed mixer using dual-gate GaAs MESFET can achieve over 10dB LO/RF isolation without hybrid, and minimize circuit size. As linear mixing signal is produced, distortions can be decreased at baseband signals. Conversion gain is achieved by mixing and amplification simultaneously. Mixer is designed to have wide band characteristics using distributed amplifier. In VCO design, Oscillator design method by large signal analysis is used to produce stable signal. Modulation/Demodulation system in baseband processor, DS/SS technique which is robust against noise and interference is used to eliminate the effect of multipath propagation. DQPSK modulation technique with M-sequences for wideband PN spreading signals is adopted because of BER characteristic and high speed digital signal transmission.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제25권1호
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• pp.53-61
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• 2014

In this paper, we present the design, fabrication and measurement of high efficiency GaN HEMT power amplifier using harmonic matching technique. In order to achieve high efficiency, harmonic load-pull simulation is performed, that is, the optimum load impedances are determined at $2^{nd}$ and $3^{rd}$ harmonic frequencies as well as at the fundamental. Then, the output matching circuit is designed based on harmonic load-pull simulation. The measurement of the fabricated power amplifier shows the linear gain of 20 dB and $P_{1dB}$(1 dB gain compression point) of 33.7 dBm at 1.85 GHz. The maximum power added efficiency(PAE) of 80.9 % is achieved at the output power of 38.6 dBm, which belongs to best efficiency performance among the reported high efficiency power amplifiers. For W-CDMA input signal, the power amplifier shows a PAE of 27.8 % at the average output power of 28.4 dBm, where an ACLR (Adjacent Channel Leakage Ratio) is measured to be -38.8 dBc. Digital predistortion using polynomial fitting was implemented to linearize the power amplifiers, which allowed about 6.2 dB improvement of an ACLR performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제23권9호
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• pp.1079-1086
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• 2012

In this paper, X-band 60 W Solid-State Power Amplifier with sequential control circuit and pulse width variation circuit for improve bias of SSPA module was designed. The sequential control circuit operate in regular sequence drain bias switching of GaAs FET. The distortion and efficiency of output signals due to SSPA nonlinear degradation is increased by making operate in regular sequence the drain bias wider than that of RF input signals pulse width if only input signal using pulsed width variation. The GaAs FETs are used for the 60 W SSPA module which is consists of 3-stage modules, pre-amplifier stage, driver-amplifier stage and main-power amplifier stage. The main power amplifier stage is implemented with the power combiner, as a balanced amplifier structure, to obtain the power greater than 60 W. The designed SSPA modules has 50 dB gain, pulse period 1 msec, pulse width 100 us, 10 % duty cycle and 60 watts output power in the frequency range of 9.2~9.6 GHz and it can be applied to solid-state pulse compression radar using pulse SSPA.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• 제14권4호
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• pp.338-347
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• 2021

In this paper, the beta-ray sensor circuit used in the true random number generator was designed using DB HiTek's 0.18㎛ CMOS process. The CSA circuit proposed a circuit having a function of selecting a PMOS feedback resistor and an NMOS feedback resistor, and a function of selecting a feedback capacitor of 50fF and 100fF. And for the pulse shaper circuit, a CR-RC2 pulse shaper circuit using a non-inverting amplifier was used. Since the OPAMP circuit used in this paper uses single power instead of dual power, we proposed a circuit in which the resistor of the CR circuit and one node of the capacitor of the RC circuit are connected to VCOM instead of GND. And since the output signal of the pulse shaper does not increase monotonically, even if the output signal of the comparator circuit generates multiple consecutive pulses, the monostable multivibrator circuit is used to prevent signal distortion. In addition, the CSA input terminal, VIN, and the beta-ray sensor output terminal are placed on the top and bottom of the silicon chip to reduce capacitive coupling noise between PCB traces.

• Journal of the Institute of Electronics Engineers of Korea SP
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• 제47권6호
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• pp.66-74
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• 2010

Recently distributed video coding (DVC) is spotlighted for the environment which has restriction in computing resource at encoder. Wyner-Ziv (WZ) coding is a representative scheme of DVC. The WZ encoder independently encodes key frame and WZ frame respectively by conventional intra coding and channel code. WZ decoder generates side information from reconstructed two key frames (t-1, t+1) based on temporal correlation. The side information is regarded as a noisy version of original WZ frame. Virtual channel noise can be removed by channel decoding process. So the performance of WZ coding greatly depends on the performance of channel code. Among existing channel codes, Turbo code and LDPC code have the most powerful error correction capability. These channel codes use stochastically iterative decoding process. However the iterative decoding process is quite time-consuming, so complexity of WZ decoder is considerably increased. Analysis of the complexity of LPDCA with real video data shows that the portion of complexity of LDPCA decoding is higher than 60% in total WZ decoding complexity. Using the HDA (Hard Decision Aided) method proposed in channel code area, channel decoding complexity can be much reduced. But considerable RD performance loss is possible according to different thresholds and its proper value is different for each sequence. In this paper, we propose an adaptive HDA method which sets up a proper threshold according to sequence. The proposed method shows about 62% and 32% of time saving, respectively in LDPCA and WZ decoding process, while RD performance is not that decreased.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제16권7호
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• pp.671-680
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• 2005

The CFL linearisation chip which is one of key devices in ultra-narrowband mobile radio transmitter using CQPSK digital modulation method is designed and implemented with $0.35{\mu}m$ CMOS technology. The reduced size and low cost of transmitter are available by the use of direct-conversion and CFL ASIC chip, which improve the power effi챠ency and linearity of transmitting path. In addition, low power operation is possible through CMOS technology The performance test results of transmitter show -25 dBc improvement of IMD level at the 3 kHz frequency offset and then satisfy FCC 47 CFR 90.210 E emission mask in the operation of CFL ASIC chip. At that time, the transmitting power is about PEP(Peak-to-Envelope Power) 5 W. The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• Journal of the Institute of Electronics Engineers of Korea TC
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• 제44권10호
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• pp.185-190
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• 2007

In this paper, minimum sampling rates and method of nonlinear characterization were suggested for low power, quasi-memoryless PAs. So far, the Nyquist rate of the input signal has been used for nonlinear PA modeling, and it is burdening Analog-to-digital converters for wideband signals. This paper shows that the input Nyquist rate sampling is not a necessary condition for successful modeling of quasi-memoryless PAs. Since this sampling requirement relives the bandwidth requirements for Analog-to-digital converters (ADCs) for feedback paths in digital pre-distortion systems, relatively low-cost ADcs can be used to identify nonlinear PAs for wideband signal transmission, even at severe aliasing conditions. Simulation results show that a generic memoryless nonlinear RF power amplifier with AMAM and AMPM distortion can be successfully identified at any sampling rates. Measurement results show the modeling error variation is less than 0.8dB over any sampling rates.