• Title/Summary/Keyword: 최소 지연

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IP Multicasting Scheme in ATM Networks (ATM망에서 다중 멀티캐스팅 서버를 이용한 IP 멀티캐스팅 방안)

  • Byeon, Tae-Yeong;Jang, Seong-Sik;Han, Gi-Jun
    • Journal of KIISE:Computer Systems and Theory
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    • v.26 no.9
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    • pp.1145-1157
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    • 1999
  • 본 논문에서는 RFC 2022에서 제안한 MARS 모델을 기반으로 하여 단일 대규모 클러스터를 가지는 ATM 망에서 다중의 멀티캐스팅 서버(MCS)를 이용한 멀티캐스팅 방안을 제안하고 그 성능을 평가하였다. 클러스터 내의 한 ATM 호스트가 특정 IP 멀티캐스트 그룹에 가입할 경우 ATM 호스트의 위치와 이미 존재하는 멀티캐스팅 서버들 사이의 전송 지연을 고려하여 가능한 한 종단간 전송 지연을 최소화하는 멀티캐스팅 서버를 선택하는 방안을 기술하였다. 이 방안은 최단거리 경로 알고리즘(shortest path algorithm)에 기반하여 최적의 MCS를 선정하고 송수신자 사이의 최소 지연을 가지는 멀티캐스트 트리를 구성한다. 다양한 망 위상에서 MCS의 분포 패턴을 다르게 할 경우에도 이 방안은 멀티캐스트 트리의 평균 전달 지연을 줄이는 것을 시뮬레이션을 통하여 확인하였다.Abstract In this paper, we proposed a scheme to support multiple MCSs over a single and large cluster in ATM networks, evaluated its performance by simulation. When an ATM host requests joining into a specific multicast group, the MARS designate a proper MCS among the multiple MCSs for the group member to minimize the average path delay between the sender and the group members. This scheme constructs a multicast tree through 2-phase partial multicast tree construction based upon the shortest path algorithm.We reduced the average path delay in multicast tree using our scheme under various cluster topologies and MCS distribution scenarios.

Routing protocol Analysis for Minimum delay Between Hierarchical node in Low Power Sensor Network (저 전력 센서 네트워크에서의 계층 노드 간 지연 감소를 위한 라우팅 프로토콜 분석)

  • Kim, Dong Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.7
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    • pp.1721-1726
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    • 2014
  • The sensor network technology for core technology of ubiquitous computing is in the spotlight recently, the research on sensor network is proceeding actively which is composed many different sensor node. The major traffic patterns of plenty of sensor networks are composed of collecting types of single directional data, which is transmitting packets from several sensor nodes to sink node. One of the important condition for design of sensor node is to extend for network life which is to minimize power-consumption under the limited resources of sensor network. In this paper analysis used routing protocols using the network simulation that was used second level cluster structure to reduce delay and power-consumption of sensor node.

Deadline-Aware Routing: Quality of Service Enhancement in Cyber-Physical Systems (사이버물리시스템 서비스 품질 향상을 위한 데드라인 인지 라우팅)

  • Son, Sunghwa;Jang, Byeong-Hoon;Park, Kyung-Joon
    • KIPS Transactions on Computer and Communication Systems
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    • v.7 no.9
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    • pp.227-234
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    • 2018
  • Guaranteeing the end-to-end delay deadline is an important issue for quality of service (QoS) of delay sensitive systems, such as real-time system, networked control system (NCS), and cyber-physical system (CPS). Most routing algorithms typically use the mean end-to-end delay as a performance metric and select a routing path that minimizes it to improve average performance. However, minimum mean delay is an insufficient routing metric to reflect the characteristics of the unpredictable wireless channel condition because it only represents average value. In this paper, we proposes a deadline-aware routing algorithm that maximizes the probability of packet arrival within a pre-specified deadline for CPS by considering the delay distribution rather than the mean delay. The proposed routing algorithm constructs the end-to-end delay distribution in a given network topology under the assumption of the single hop delay follows an exponential distribution. The simulation results show that the proposed routing algorithm can enhance QoS and improve networked control performance in CPS by providing a routing path which maximizes the probability of meeting the deadline.

A Study on Rock Fragmentation Variation by Delay Time (지연시차에 따른 파쇄입도 변화에 관한 연구)

  • Jin, Yeon-Ho;Min, Hyung-Dong;Park, Yoon-Suk;Heo, Eui-Haeng;Choi, Sung-Oong;Lee, Seung-Joong
    • Explosives and Blasting
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    • v.32 no.3
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    • pp.1-9
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    • 2014
  • Since the rock fragmentation from a bench blasting can affect the subsequent processes including loading, hauling and crushing, its control is essential for the assessment of blasting efficiency as well as production cost. In this study, the delay time could be precisely controlled by using electronic detonators. The rock fragmentations resulted from the blastings with different delay times of 1, 2, 3, 4, 5, 7 and 10ms per each meter of burden were measured from full scale field tests in a limestone mine. The results showed that the optimum delay time for minimum fragmentation was approximately 6ms/m. From the analysis of fragmentation size distribution, it was possible to find that delay time can be a parameter on rock fragmentation and thus it would be possible to control rock fragmentation by adjusting delay time.

Measurement of Autoignition Temperature of n-Propanol and Formic acid System (n-Propanol과 Formic acid계의 최소자연발화온도의 측정)

  • Cho, Young-Se;Ha, Dong-Myeong
    • Fire Science and Engineering
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    • v.27 no.5
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    • pp.64-69
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    • 2013
  • The autoignition temperatures (AITs) of solvent mixture was important index for the safe handling of flammable liquids which constitute the solvent mixtures. This study measured the AITs and ignition delay time for n-propanol and formic acid system by using ASTM E659 apparatus. The AITs of n-Propanol and Formic acid which constituted binary system were $435^{\circ}C$ and $498^{\circ}C$, respectively. The experimental AITs of n-propanol and formic acid system were a good agreement with the calculated AITs by the proposed equations with a few A.A.D. (average absolute deviation). And n- Propanol and formic acid system was shown the minimum autoignition temperature behavior (MAITB).

Response Time Analysis of Web Service Systems with Mixedly Distributed Stochastic Timed Net (혼합 분포 확률 시간 넷을 이용한 웹 서비스 시스템의 응답 시간 분석)

  • Yim, Jae-Geol;Do, Jae-Su;Shim, Kyu-Bark
    • Journal of Korea Multimedia Society
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    • v.9 no.11
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    • pp.1503-1514
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    • 2006
  • Today, consumers can access Internet from everywhere, therefore most commercial and other organizations provide their services on the Web. As the result, countless Web service systems are already on the Internet and more systems are under construction. Therefore, many researches of verifying that the system to be constructed will not have any deadlock and will run successfully without any problem at the early stage of design have been performed. Several Petri net based verification methods have also been published. However, they have focused on building Petri net models of Web service systems and none of them introduces efficient analysis methods. As a mathematical technique with which we can find the minimum duration time needed to fire all the transitions at least once and coming back to the initial marking in a timed net, the minimum cycle time method has been widely used in computer system analysis. A timed net is a modified version of a Petri net where a transition is associated with a delay time. A delay time used in a timed net is a constant even though the duration time associated with an event in the real world is a stochastic number in general. Therefore, this paper proposes 'Mixedly Distributed Stochastic Timed Net' where a transition can be associated with a stochastic number and introduce a minimum cycle time analysis method for 'Mixedly Distributed Stochastic Timed Net'. We also introduce a method of analysing a Web service system's response time with the minimum cycle time analysis method for 'Mixedly Distributed Stochastic Timed Net.'.

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Improved Unslotted IEEE 802.15.4 Algorithm for HAN in Smart Grids (스마트그리드 HAN을 위한 개선된 Unslotted IEEE 802.15.4 알고리즘)

  • Hwang, Sung Ho
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.15 no.3
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    • pp.1711-1717
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    • 2014
  • There have been many studies on IEEE 802.15.4 for home area networks(HAN) in Smart Grids. Existing unslotted or slotted IEEE 802.15.4 has almost not met strict conditions of the U.S. Department Of Energy(DOE). This study proposed a improved algorithm that reduces collisions, delay time and changes in the delay time. For this purpose, numbers were given to nodes to make the transmission in the order of the node numbers. Since the probability of the occurrence of collisions would decrease compared to random transmission if the nodes were given numbers, Backoff time was set at 0. In the proposed Numbered-Unslotted-ZeroBackoff algorithm, when the packet size was 133 octets and less than 180 packets per second occurred, it was found that packet delivery ratio was over 99.99%, and that all the maximum delay, the mean delay and the minimum delay were less than 0.02 seconds. This paper could confirm that the algorithm proposed in this study met the strict conditions of the DOE.

Memory Controller Architecture with Adaptive Interconnection Delay Estimation for High Speed Memory (고속 메모리의 전송선 지연시간을 적응적으로 반영하는 메모리 제어기 구조)

  • Lee, Chanho;Koo, Kyochul
    • Journal of IKEEE
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    • v.17 no.2
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    • pp.168-175
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    • 2013
  • The delay times due to the propagating of data on PCB depend on the shape and length of interconnection lines when memory controllers and high speed memories are soldered on the PCB. The dependency on the placement and routing on the PCB requires redesign of I/O logic or reconfiguration of the memory controller after the delay time is measured if the controller is programmable. In this paper, we propose architecture of configuring logic for the delay time estimation by writing and reading test patterns while initializing the memories. The configuration logic writes test patterns to the memory and reads them by changing timing until the correct patterns are read. The timing information is stored and the configuration logic configures the memory controller at the end of initialization. The proposed method enables easy design of systems using PCB by solving the problem of the mismatching caused by the variation of placement and routing of components including memories and memory controllers. The proposed method can be applied to high speed SRAM, DRAM, and flash memory.

Convergence Characteristics of Compensation Algorithm in Frequency Selective Fading Channel (주파수 선택성 페이딩 채널에서 보상 알고리즘의 수렴특성)

  • Lee, Seung-Dae
    • Journal of the Korea Computer Industry Society
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    • v.8 no.4
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    • pp.263-268
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    • 2007
  • It applied the linear tapped delay line structure to the least mean square algorithm and the recursive least square algorithm it investigated the mean square error characteristics of compensation algorithm. The purpose of this paper is to propose multi-tap update algorithm, which is superior to compensation capacity of data, and then compare and analyze it from the perspective of convergence characteristics at time invariant transmission channel and frequency selective fading channel.

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A Study on the VLSI Systolic Array Implementation of 2-Dimensional FIR Digital Filter (2-Dimensional FIR 디지털 필터의 VLSI 시스토릭 어레이 구조 실험에 관한 연구)

  • 김수현;문대철
    • The Journal of the Acoustical Society of Korea
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    • v.12 no.4
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    • pp.32-38
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    • 1993
  • 2-D FIR 필터를 시스토릭 어레이 구조로 실현하는 방법을 제시하였다. 시스토릭 어레이는 1-D FIR 필터로 부분 실현한 후 병렬연겨랗여 구현하였다. 부분 실현한 시스토릭 어레이의 마지막 입력신호를 다음 단의 입력에 직접연결시킴으로써 입력 지연에 사용되는저장요소를 절약 시킨다. 1-D 시스ㅏ토릭 어레이는 지역통신 접근에 의해 DG를 설계한 후 SFG로으ㅟ 사상을 통해 유도하였다. 유도된 SFG는 DG의 노드가 보다 적은수의 PE에 사상됨으로써 PE의 이용률을 개선할 수 잇다. 유도된 구조는 매우 간단하며, 입력 샘플이 공급되어지면 매 샘플링 기간마다 새로운 출력을 얻는 매우 SHB은 데이터 비율(data rate)을 갖는다. 시스토릭 어레이는 규칙적이고, 모듈성이며, local interconnection, highly synchronized multiprocessing 의 특징을 갖기 때문에 VLSI 실현에 매우 적합하다. PE 셀 구조는 높은 처리율, 최소 계산시간과 최소 파이프라인 주기를 갖도록 설계하였다.

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