• Journal of Advanced Marine Engineering and Technology
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• v.38 no.1
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• pp.8-14
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• 2014

This research designed Waste Heat Recovery System(WHRS) generation system of 250kW whose working fluid is R-245fa and studied on cycle characteristics by superheater organization. It simulated two conditions; series connection and parallel connection between superheater and evaporator. In simulation of series connection of superheater and evaporator, output of 4.7% could be improved because of the increase of enthalpy by overheating of working fluid. When setting 250kW for target output, cycle flux could be reduced by 4.1%. When setting 250kW as a target output of cycle In parallel connection simulation of superheater and evaporator, cycle flux was reduced as flux of heat source fluid for superheater was increased. So, the maximum 7.9% of working fluid pump's electric power was reduced and there was no big change in cycle efficiency and net efficiency by flux ratio.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.142-147
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• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• Transactions of the Korean Society of Mechanical Engineers
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• v.12 no.1
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• pp.48-52
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• 1988

For the refrigeration system using the reversed Carnot cycle, maximum conditions of effectiveness and available energy output are studied with taking into account of the heat transfer between heat sources and the cycle, and of the heat loss due to heat leakage into the cold heat source. The extremum of the effectiveness exists for variables T$_{l}$ and T$_{L}$. Therefore the desirable results in engineering applications that available energy output is not zero under maximum condition of the effectiveness are obtained. In addition, the extremum of the available energy output does not exist for the variable T$_{l}$ but does for the variable T$_{L}$. As the heat loss increases, the available energy output and the effectiveness decrease, the regions of T$_{l}$ and T$_{L}$ where the refrigeration system is possible to operate become smaller.aller.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.1
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• pp.77-86
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• 1992

This paper discusses the thermodynamic study on the suction cooling-steam injected gas turbine cycle. The aim of this study is to improve the thermal efficiency and the specific output by steam injection produced by the waste heat from the waste heat recovery boiler and by cooling compressor inlet air by an ammonia absorption-type suction cooling system. The operating region of this newly devised cycle depends upon the pinch point limit and the outlet temperature of refrigerator. The higher steam injection ratio and the lower the evaporating temperature of refrigerant allow the higher thermal efficiency and the specific output. The optimum pressure ratios and the steam injection ratios for the maximum thermal efficiency and the specific output can be found. It is evident that this cycle considered as one of the most effective methods which can obtain the higher thermal efficiency and the specific output comparing with the conventional simple cycle and steam injected gas turbine cycle.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.3
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• pp.293-299
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• 2012

The thermodynamic efficiency characteristics of R245fa and water as working fluids have been analyzed for the electricity generation system applying the Rankine cycle to recover the waste heat of the exhaust gas from a diesel engine for the propulsion of a large ship. The theoretical calculation results showed that the cycle, system, and total efficiencies were improved as the turbine inlet pressure was increased for R245fa at a fixed mass flow rate. In addition, the net work rate generated by the Rankine cycle was elevated with increasing turbine inlet pressure. In the case of water, however, the maximum system efficiencies were demonstrated at relatively small ratios of mass flow rate and turbine inlet pressure, respectively, compared to those of R245fa. The optimized values of the net power of the cycle, system efficiency, and total efficiency for water had relatively large values compared to those of R245fa.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7A
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• pp.547-556
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• 2003

This paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for low-area elliptic curve cryptographic processor. The proposed arithmetic unit, which is linear feed back shift register (LFSR) architecture, is designed by using hardware sharing between the binary GCD algorithm and the most significant bit (MSB)-first multiplication scheme, and it can perform both division and multiplication in GF(2$^{m}$ ). In other word, the proposed architecture produce division results at a rate of one per 2m-1 clock cycles in division mode and multiplication results at a rate of one per m clock cycles in multiplication mode. Analysis shows that the computational delay time of the proposed architecture, for division, is less than previously proposed dividers with reduced transistor counts. In addition, since the proposed arithmetic unit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed novel architecture can be used for both division and multiplication circuit of elliptic curve cryptographic processor. Specially, it is well suited to low-area applications such as smart cards and hand held devices.

• Journal of the Korean Solar Energy Society
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• v.30 no.5
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• pp.63-68
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• 2010

To guarantee life time more than 20 years for manufacturer without stopping photovoltaic(PV) system, it is really important to test the module in realistic time and condition compared to outside weather. In here, we tested PV modules in highly stressed condition compared to IEC standards. In IEC 61215 and IEC 61646 standards, damp-heat, thermal cycle(TC200) and mechanical test are main test items for evaluating long-term durability of PV module in controlled temperature and humidity condition. So in this paper, we have lengthened the test time for TC200 and damp-heat test and increased the loading stress on surface of module. Through this test, we can get some clue of proper the method for measuring realistic life cycle of PV modules and suggested the minimum time for PV test method. The detail description is specified as the following paper.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.9 no.1
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• pp.74-78
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• 1976

In this paper, the author experimented, by using the C. F. R. engine, how the functions of engine is changed when the compression ratio is raised. In the process of these experiments, by using three kinds of fuel, such as cetane number 95, 61, 33, and set the engine speed as 900 r. p. m., fuel injection time is determined as B. T. D. C. $13^{\circ}$. As the result of test, the best compression ratio is disernable in proportion to each fuel, and acknowledges that if the higher compression ratio were to exist other than the above one, efficiency of heat gets rather lower, and that the maximum output of engine decreases. Andthe best compression ratio changed according to supply calorie per each hour, and this change is more remarkable in the fuel of low cetane number. Consequently, the best compression ratio cannot be regardless of output in the fuel of low cetane number.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1047-1054
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• 2004

In this paper, we present two systolic arrays for computing multiplications in CF(2$\^$m/) generated by an irreducible all one polynomial (AOP). The proposed two systolic mays have parallel-in parallel-out structure. The first systolic multiplier has area complexity of O(㎡) and time complexity of O(1). In other words, the multiplier consists of m(m+1)/2 identical cells and produces multiplication results at a rate of one every 1 clock cycle, after an initial delay of m/2+1 cycles. Compared with the previously proposed related multiplier using AOP, our design has 12 percent reduced hardware complexity and 50 percent reduced computation delay time. The other systolic multiplier, designed for cryptographic applications, has area complexity of O(m) and time complexity of O(m), i.e., it is composed of m+1 identical cells and produces multiplication results at a rate of one every m/2+1 clock cycles. Compared with other linear systolic multipliers, we find that our design has at least 43 percent reduced hardware complexity, 83 percent reduced computation delay time, and has twice higher throughput rate Furthermore, since the proposed two architectures have a high regularity and modularity, they are well suited to VLSI implementations. Therefore, when the proposed architectures are used for GF(2$\^$m/) applications, one can achieve maximum throughput performance with least hardware requirements.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.