• Title/Summary/Keyword: 처리 지연

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인터넷 쇼핑몰에서의 불평행동 유형에 따른 효과적인 불평처리방안

  • Park, Myeong-Ho;Jang, Yeong-Hye
    • Proceedings of the Korean DIstribution Association Conference
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    • 2006.08a
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    • pp.21-46
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    • 2006
  • 본 연구에서는 인터넷 쇼핑몰에서 불만족을 경험한 고객들의 불평요인 및 불평행동유형을 파악하고, 쇼핑몰 업체의 불평처리방법에 대한 평가를 바탕으로 효과적인 불평처리방안을 제시하였다. 연구 결과 불평행동을 하는 고객의 유형은 직접행동파, 사적행동파, 소극행동파, 적극행동파 등으로 구분되었다. 이 가운데 사적행동파가 가장 높게 나타나 인터넷 환경에서는 사적행동파에 대한 효과적인 불평처리 방안에 관한 노력이 가장 필요한 것으로 확인되었다. 직접행동파는 해당 쇼핑몰 업체에게 직접 문제해결을 요구하기 때문에 불평처리에 대한 공정성, 불평 후 만족과 충성도 측면에서 가장 효과적인 것으로 확인되었다. 그리고 고객의 모든 불평행동유형에서 가장 심각한 불만족 요인으로는 배송오류 및 지연과 제품결함인 것으로 확인되었지만, 사적행동파와 소극행동파는 부정확한 정보제공과 과장광고 등을 심각하게 생각하고 있었다. 인터넷 쇼핑몰 업체는 불평고객들의 불평해결을 위해 직접적인 접촉을 할 경우 가장 효과적인 불평처리를 할 수 있기 때문에 사적행동파와 소극행동파의 불평행동을 유발하기 위한 노력이 필요하다. 또한 쇼핑몰 관리자의 불친절 및 반응은 심각한 불만족 요인은 아니지만, 배송오류 및 지연과 제품결함과 같은 심각한 불만족요인에 대해서는 직접적인 사과 및 쇼핑몰 관리자의 친절한 태도를 포함하여 현금 환불 등 불평처리를 해야 한다. 그리고 고객의 관점에서 인터넷 쇼핑몰을 보다 편리하고 유용하게 설계할 필요가 있다.

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Implementation of T-Cache engine based on Primary key for enhancing System Performance (시스템 성능 향상을 위한 Primary key 기반 T-Cache 설계 및 구현)

  • Kang, Hyung-Man;Lee, Un-Bae
    • Proceedings of the Korea Information Processing Society Conference
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    • 2011.04a
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    • pp.1195-1198
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    • 2011
  • 인터넷 및 스마트폰 등 모바일 시장의 급성장으로 다양한 채널이 발달하여 금융거래가 급속하게 증가함으로써 시스템 자원이 부족하고 또한, 급변하는 금융시장에서 경쟁력을 잃지 않기 위하여 국내의 금융권 시스템들은 차세대를 진행하면서 경쟁적으로 프레임웍을 도입하여 프로젝트를 진행하였거나 또는 진행하고 있다. 프레임웍은 요청한 거래를 검증하고, 처리하여 결과를 반환할 수 있도록 여러 가지 편의성을 제공하지만, 동일 테이블 데이터를 매 거래마다 데이터베이스를 조회함으로써 데이터베이스 서버의 부하가 증가하고 거래 처리가 지연되는 문제점이 있다. 본 논문에서는 프레임웍 기반의 매 거래마다 동일 데이터를 데이터베이스로부터 질의함으로써 발생하는 거래처리 지연을 극복하고 보다 빠른 응답 처리를 위하여 1) 대부분 조회를 처리하는 테이블에 대해서 테이블 단위로 Primary key을 이용하여 공유메모리에 저장하고, 많은 응용프로그램 간에 공유하는 방식으로 거래를 처리함으로써 디스크 I/O나 네트워크 I/O, DBMS 자체 프로세싱을 크게 감소하여 전제적으로 시스템의 성능을 향상시키며 2) 공유메모리에 저장하고 있는 데이터와 데이터베이스 테이블에 저장된 데이터간의 동기화를 지원하는 Primary key 기반 T-Cache(Table Cache) 알고리즘을 제안한다.

Reducing False Alarm and Shortening Worm Detection Time in Virus Throttling (Virus Throttling의 웜 탐지오판 감소 및 탐지시간 단축)

  • Shim Jae-Hong;Kim Jang-bok;Choi Hyung-Hee;Jung Gi-Hyun
    • The KIPS Transactions:PartC
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    • v.12C no.6 s.102
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    • pp.847-854
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    • 2005
  • Since the propagation speed of the Internet worms is quite fast, worm detection in early propagation stage is very important for reducing the damage. Virus throttling technique, one of many early worm detection techniques, detects the Internet worm propagation by limiting the connection requests within a certain ratio.[6, 7] The typical throttling technique increases the possibility of false detection by treating destination IP addresses independently in their delay queue managements. In addition, it uses a simple decision strategy that determines a worn intrusion if the delay queue is overflown. This paper proposes a two dimensional delay queue management technique in which the sessions with the same destination IP are linked and thus a IP is not stored more than once. The virus throttling technique with the proposed delay queue management can reduce the possibility of false worm detection, compared with the typical throttling since the proposed technique never counts the number of a IP more than once when it chicks the length of delay queue. Moreover, this paper proposes a worm detection algorithm based on weighted average queue length for reducing worm detection time and the number of worm packets, without increasing the length of delay queue. Through deep experiments, it is verified that the proposed technique taking account of the length of past delay queue as well as current delay queue forecasts the worn propagation earlier than the typical iuぉ throttling techniques do.

Edge to Edge Model and Delay Performance Evaluation for Autonomous Driving (자율 주행을 위한 Edge to Edge 모델 및 지연 성능 평가)

  • Cho, Moon Ki;Bae, Kyoung Yul
    • Journal of Intelligence and Information Systems
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    • v.27 no.1
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    • pp.191-207
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    • 2021
  • Up to this day, mobile communications have evolved rapidly over the decades, mainly focusing on speed-up to meet the growing data demands of 2G to 5G. And with the start of the 5G era, efforts are being made to provide such various services to customers, as IoT, V2X, robots, artificial intelligence, augmented virtual reality, and smart cities, which are expected to change the environment of our lives and industries as a whole. In a bid to provide those services, on top of high speed data, reduced latency and reliability are critical for real-time services. Thus, 5G has paved the way for service delivery through maximum speed of 20Gbps, a delay of 1ms, and a connecting device of 106/㎢ In particular, in intelligent traffic control systems and services using various vehicle-based Vehicle to X (V2X), such as traffic control, in addition to high-speed data speed, reduction of delay and reliability for real-time services are very important. 5G communication uses high frequencies of 3.5Ghz and 28Ghz. These high-frequency waves can go with high-speed thanks to their straightness while their short wavelength and small diffraction angle limit their reach to distance and prevent them from penetrating walls, causing restrictions on their use indoors. Therefore, under existing networks it's difficult to overcome these constraints. The underlying centralized SDN also has a limited capability in offering delay-sensitive services because communication with many nodes creates overload in its processing. Basically, SDN, which means a structure that separates signals from the control plane from packets in the data plane, requires control of the delay-related tree structure available in the event of an emergency during autonomous driving. In these scenarios, the network architecture that handles in-vehicle information is a major variable of delay. Since SDNs in general centralized structures are difficult to meet the desired delay level, studies on the optimal size of SDNs for information processing should be conducted. Thus, SDNs need to be separated on a certain scale and construct a new type of network, which can efficiently respond to dynamically changing traffic and provide high-quality, flexible services. Moreover, the structure of these networks is closely related to ultra-low latency, high confidence, and hyper-connectivity and should be based on a new form of split SDN rather than an existing centralized SDN structure, even in the case of the worst condition. And in these SDN structural networks, where automobiles pass through small 5G cells very quickly, the information change cycle, round trip delay (RTD), and the data processing time of SDN are highly correlated with the delay. Of these, RDT is not a significant factor because it has sufficient speed and less than 1 ms of delay, but the information change cycle and data processing time of SDN are factors that greatly affect the delay. Especially, in an emergency of self-driving environment linked to an ITS(Intelligent Traffic System) that requires low latency and high reliability, information should be transmitted and processed very quickly. That is a case in point where delay plays a very sensitive role. In this paper, we study the SDN architecture in emergencies during autonomous driving and conduct analysis through simulation of the correlation with the cell layer in which the vehicle should request relevant information according to the information flow. For simulation: As the Data Rate of 5G is high enough, we can assume the information for neighbor vehicle support to the car without errors. Furthermore, we assumed 5G small cells within 50 ~ 250 m in cell radius, and the maximum speed of the vehicle was considered as a 30km ~ 200 km/hour in order to examine the network architecture to minimize the delay.

Mechanism of Multimedia Synchronization using Delay Jitter Time (지연지터시간을 이용한 멀티미디어 동기화 기법)

  • Lee, Keun-Wang;Jun, Ho-Ik
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.11
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    • pp.5512-5517
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    • 2012
  • In this paper we suggest multimedia synchronization model that is based on the Petri-net and services desirable quality of service requirement. Proposed model applies variable buffer which can be allowed, and then it presents high quality of service and real time characteristics. This paper decreases the data loss resulted from variation of delay time and from loss time of media-data by means of applying delay jitter in order to deal with synchronization interval adjustment. Plus, the mechanism adaptively manages the waiting time of smoothing buffer, which leads to minimize the gap from the variation of delay time. The proposed paper is suitable to the system which requires the guarantee of high quality of service and mechanism improves quality of services such as decrease of loss rate, increase of playout rate.

The Research about Voice Transmission between CDMA Network and PSTN Network Using CDMA Circuit Data Service (CDMA 회선 데이터 서비스를 이용한 CDMA망과 PSTN 망간의 음성 전송에 관한 연구)

  • Park, Yong-Seok;Ahn, Jae-Hwan;Ryou, Jae-Cheol
    • The KIPS Transactions:PartC
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    • v.15C no.5
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    • pp.367-374
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    • 2008
  • To realize the voice privacy between CDMA mobile phone and PSTN terminal, the voice frames shall be transmitted transparently between the heterogeneous networks. For satisfying this requirement, we propose the method which transmits voice frames using the CDMA circuit data channel in real time. In this paper we analyze the causes of voice delay which occurs during voice transmission using circuit data channel. And in order to overcome this kind of delay, the technique controlling the TCP control flag and the variable audio block construction algorithm according to the vocoder output rate are proposed. As a result of experimenting by applying the proposed method, we confirmed that the transit delay was improved with about average 70%.

Design of a Low-Power Carry Look-Ahead Adder Using Multi-Threshold Voltage CMOS (다중 문턱전압 CMOS를 이용한 저 전력 캐리 예측 가산기 설계)

  • Kim, Dong-Hwi;Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.15A no.5
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    • pp.243-248
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    • 2008
  • This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

Efficient Processor Allocation based on Join Selectivity in Multiple Hash Joins using Synchronization of Page Execution Time (페이지 실행시간 동기화를 이용한 다중 해쉬 결합에서 결합률에 따른 효율적인 프로세서 할당 기법)

  • Lee, Gyu-Ok;Hong, Man-Pyo
    • Journal of KIISE:Computer Systems and Theory
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    • v.28 no.3
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    • pp.144-154
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    • 2001
  • 다중 결합 질의에 포함된 다수의 결합 연산지를 효율적으로 처리하기 위해 서는 효율적인 병렬 알고리즘이 필요하다. 최근 다중 해쉬 결합 질의의 처리를 위해 할당 트리를 이용한 방법이 가장 우수한 것으로 알려져 있다. 그러나 이 방법은 실제 결합 시에 할당 트리의 각 노드에서 필연적인 지연이 발생되는 데 이는 튜플-시험 단계에서 외부 릴레이션을 디스크로부터 페이지 단위로 읽는 비용과 이미 읽는 페이지에 대한 해쉬 결합 비용간의 차이에 의해 발생하게 된다. 이들 사이의 실행시간을 가급적 일치시키기 위한 '페이지 실행시간 동기화'기법이 제안되었고 이를 통해 할당 트리 한 노드 실행에 있어서의 지연 시간을 줄일 수 있었다. 하지만 지연 시간을 최소화하기 위해 할당되어질 프로세서의 수 즉, 페이지 실행시간 동기화 계수(k)는 실제 결합 시의 결합률에 따라 상당한 차이를 보이게 되고 결국, 이 차이를 고려하지 않은 다중 해쉬 결합은 성능 면에서 크게 저하될 수밖에 없다. 본 논문에서는 결합 이전에 어느 정도의 결합률을 예측할 수 있다는 전제하에 다중 해쉬 결합 실행 시에 발생할 수 있는 지연 시간을 최소화 할 수 있도록 결합률에 따라 최적의 프로세서들을 노드에 할당함으로서 다중 해쉬 결합의 실행 성능을 개선하였다. 그리고 분석적 비용 모형을 세워 기존 방식과의 다양한 성능 분석을 통해 비용 모형의 타당성을 입증하였다.

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High Performance Routing Engine for an Advanced Input-Queued Switch Fabric (고속 입력 큐 스위치를 위한 고성능 라우팅엔진)

  • Jeong, Gab-Joong;Lee, Bhum-Cheol
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.264-267
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    • 2002
  • This paper presents the design of a pipelined virtual output queue routing engine for an advanced input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array (FPGA) chip with a 77MHz operating frequency, 16$\times$16 switch size, and 2.5Gbps/port speed.

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Consideration about Traffic Characteristics of DV and MPEG2 Streams on IP over ATM (IP over ATM 상에서 DV와 MPEG2 스트림의 트래픽 특성 고찰)

  • Lee, Jae-Kee;Saito, Tadao
    • The KIPS Transactions:PartC
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    • v.10C no.7
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    • pp.937-942
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    • 2003
  • In this paper, we measured and examined RTT delays and packet losses according to the changes of stationary loads for two typical stream-type traffics, a DV and a MPGE2 on the R&D Gigabit Network testbed, JGN. As the result of our actual measurements, we realized that the packet size of stationary load have no effects on a DV and a MPGE2 stream on the very high-speed network(50Mbps, IP over ATM). When its bandwidth and stationary load exceeds 95% of network bandwidth, packet losses appeared and RTT delay increased rapidly. Also we realized that the number and size of Receive & Transmit buffer on the end systems have no effects on packet losses and RTT delays.