• Title/Summary/Keyword: 집적도

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미래사회를 지탱하는 파워디바이스 기술의 진전

  • 대한전기협회
    • JOURNAL OF ELECTRICAL WORLD
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    • s.323
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    • pp.69-75
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    • 2003
  • 불투명한 경제정세의 와중에서도 전기에너지를 지탱하는 근간이 되는 파워 일렉트로닉스 분야는 확실히 그 기술개발을 향상시켜 오고 있다. 특히 파워디바이스는, 지구환경과 생활환경을 보다 쾌적하게 하기 위하여 인버터 장치 등의 각종 전력절약기기와 풍력$\cdot$태양광$\cdot$연료전지 등 클린에너지의 전력제어장치에 없어서는 안되는 반도체디바이스로 성장했다. 파워디바이스 중에서도 IGBT(Insulated Gate Bipolar Transistor)의 기술혁신은 요 20년 사이에 비약적인 성과를 거두었다. 1980년대에 제품화된 IGBT는, 반도체메모리의 초미세가공기술을 도입하면서 $5{\mu}m$에서 서브미크론의 디자인툴로 발전하여, 2000년대에 들어 칩의 전류밀도는 약 2배, 포화전압은 약 $65\%$까지 개량되었다. 이와 같은 IGBT의 변천은, 전력손실을 대폭적으로 저감시켜 에너지절약기기의 전력변환효율 향상에 공헌하고 있다. 파워디바이스의 기술진보에서 또 한 가지 잊지 말아야 할 것은 주변회로의 집적화(集積化)에 의한 고성능$\cdot$고기능화이다. 최근의 인버터용 파워디바이스로 가장 많이 사용되고 있는 파워모듈은, IGBT등의 파워칩과 그 주변회로와의 컬래버레이션에 의한 제품이다. 다시 말하면 구동회로, 전류$\cdot$전압$\cdot$온도센서 및 그것들의 보호회로가 IC(집적회로)에 편입되어 고기능$\cdot$소형화를 촉진시키고 있다. 구동회로는 LVIC (저전압집적회로)에서 HVIC(고전압집적회로)로 발전하여 전류$\cdot$온도 등의 각종 센서도 동일 칩에 설계할 수 있게 되었다. 또 센싱이나 보호기능뿐만이 아니라 출력전류의 제어를 위한 연산기능과 di/dt의 제어기능이 내장되도록 되어 있어 보다. 고성능의 인텔리전트 파워모듈(IPM)이라고 불리우는 새로운 개념의 파워디바이스가 실현되었다. 또한 패키지 기술도 내부배선 인덕턴스의 저감과 트랜스퍼 몰드패키지의 개발로, 소형화뿐만이 아니라 파워칩의 성능$\cdot$기능을 충분히 발휘할 수 있도록 개발이 적극적으로 추진되고 있다.

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The Impedance Analysis of Multiple TSV-to-TSV (다중(multiple) TSV-to-TSV의 임피던스 해석)

  • Lee, Sihyun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.7
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    • pp.131-137
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    • 2016
  • In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.

Full-Custom Design of a Serial Peripheral Interface Circuit for CMOS RFIC Testing (CMOS RF 집적회로 검증을 위한 직렬 주변 인터페이스 회로의 풀커스텀 설계)

  • Uhm, Jun-Whon;Lee, Un-Bong;Shin, Jae-Wook;Shin, Hyun-Chol
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.9
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    • pp.68-73
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    • 2009
  • This paper presents an easily modifiable structure of a serial peripheral interface (SPI) that is suitable for efficient testing of CMOS RF integrated circuits. The proposed SPI Is designed so that the address size and the accompanying software can be easily adjusted and modified according to the requirements and complexity of RF IC's under development. The hardware architecture and software algorithm to achieve the flexibility are described. The proposed SPI is fabricated in $0.13{\mu}m$ CMOS and successfully verified experimentally with a 2.7GHz fractional-N delta-sigma frequency synthesizer as a device under test.

Ultimate Heterogeneous Integration Technology for Super-Chip (슈퍼 칩 구현을 위한 헤테로집적화 기술)

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.17 no.4
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    • pp.1-9
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    • 2010
  • Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

Depth Extraction of Integral Imaging Using Correlation (상관관계를 활용한 집적 영상의 깊이 추출 방법)

  • Kim, Youngjun;Cho, Ki-Ok;Kim, Cheolsu;Cho, Myungjin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.7
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    • pp.1369-1375
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    • 2016
  • In this paper, we present a depth extraction method of integral imaging using correlation between elemental images with phase only filter. Integral imaging is a passive three-dimensional (3D) imaging system records ray information of 3D objects through lenslet array by 2D image sensor, and displays 3D images by using the similar lenslet array. 2D images by lenslet array have different perspectives. These images are referred to as elemental images. Since the correlation can be calculated between elemental images, the depth information of 3D objects can be extracted. To obtain high correaltion between elemental images effectively, in this paper, we use phase only filter. Using this high correlation, the corresponding pixels between elemental images can be found so that depth information can be extracted by computational reconstruction technique. In this paper, to prove our method, we carry out optical experiment and calculate Peak Sidelobe Ratio (PSR) as a correlation metric.

Visual quality enhancement of three-dimensional photon-counting integral imaging using background noise removal algorithm (배경 잡음 제거 알고리즘을 적용한 3차원 광자 계수 집적 영상의 화질 향상)

  • Cho, Ki-Ok;Kim, Young jun;Kim, Cheolsu;Cho, Myungjin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.7
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    • pp.1376-1382
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    • 2016
  • In this paper, we present a visual quality enhancement technique for conventional three-dimensional (3D) photon counting integral imaging using background noise removal algorithm. Photon counting imaging can detect a few photons from desired objects and visualize them under severely photon-starved conditions such as low light level environment. However, when a lot of photons are generated from background, it is difficult to detect photons from desired objects. Thus, the visual quality of the reconstructed image may be degraded. Therefore, in this paper, we propose a new photon counting imaging method that removes unnecessary background noise and detects photons from only desired objects. In addition, integral imaging can be used to obtain 3D information and visualize the 3D image by statistical estimations such as maximum likelihood estimation. To prove and evaluate our proposed method, we implement the optical experiment and calculate mean square error.