• Journal of the Institute of Convergence Signal Processing
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• v.1 no.2
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• pp.131-137
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• 2000

In this paper, as a compatible software radio transmission system, Digital-Radio conversion system which can directly change the digital signal generated by the logic circuit into radio signal is proposed. By the vector synthesis method, the digital signals can change directly into radio signal. If such a circuit is realized, RF circuit and an antenna can be composed by the simple one device, and the radio is directly controlled and performed by the software processing which is the essence of software radio. This Digital-Radio conversion system of this paper give many number of communication channels being offered by PN code and offer a hardware design flexibility by digitization, therefore it decrease the percentage ratio of hardware of system and give a more flexible function of software basis. In this paper, the principle of digital to radio signal generation algorithm is explained and the performance characteristics of proposed algorithm is shown in time base by the computer simulation method.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.784-787
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• 1999

This paper describes a direct digital frequency synthesizer using the CORDIC algorithm, which can be implemented efficiently for a digital sinusoid synthesis. To optimize the hardware design parameters, we perform numerical analysis of the quantization effects for the CORDIC-based architecture. A pipelined architecture is employed to obtain a high data throughput,. We estimate and summarize its hardware costs for a variable accuracy, and a CORDIC-based architecture for 9 bit accuracy is emulated in FPGA.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.5
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• pp.775-784
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• 2010

In this paper we propose a design method of X band frequency hopping synthesizer in terms of phase noise and settling time with DDS driven PLL architecture, which has the advantages of high frequency resolution, fast settling time and small size. In addition, a noble method is proposed to remove the synthesizer output spurious signals due to superposition effect of DDS. The spurious signal which depend on its normalized frequency of DDS, can be dominant if they occur within the PLL loop bandwidth. We verify that the sources of that spurious signals are quasi-amplitude modulation and superposition effect, and suggest that such signals can be eliminated by intentionally creating frequency errors in the developed synthesizer.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.946-949
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• 2003

In this paper, a DDFS(Direct Digital Frequency Synthesis)chip has been designed focusing on the reduction of ROM size and implemented using FPGA. When calculating the sine value for the input phase value, we used the Taylor series expansion approximation method to reduce the number of addresses of ROM. We also used the piecewise straight line approximation method, ie, the stored value int the ROM is the difference of the sine value and the straight line approximation. Using this method, we could reduce four bits for each ROM data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.10
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• pp.966-980
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• 2011

Radar receiving echo signal provides target information - range, velocity and position by signal magnitude and Doppler shift, which are determined by target reflection characteristics and target maneuver. Target angle error is extracted from the magnitude ratio of difference channel to sum channel. In this paper, we introduce a radar Return Signal Simulation Equipment(RSSE) which is implemented for the purpose of performance analysis and evaluation of phased array multi-function radar(MFR). It generates multi-target environment with jamming signals using MC-DDS (Multi-Channel Direct Digital Synthesis), and has scalability by using the efficient hardware configuration. The performance of the developed RSSE has been evaluated under various test environments. Especially, we proved that required target detection performance is achieved by RSP(Radar Signal Processor) interfaced RSSE configuration.

• Journal of Internet Computing and Services
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• v.24 no.5
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• pp.37-50
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• 2023

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1190-1196
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• 2014

This paper presents the design of a Frequency Modulated Continuous Wave(FMCW) radar altimeter with wide altitude range and low measurement errors. Wide altitude range is achieved by employing the optic delay in the transmitting path to reduce the dynamic range of measuring altitude. Transmitting power and receiver gain are also controlled to have the dynamic range of the received power be reduced. In addition, low measurement errors are obtained by improving the sweep linearity using the Direct Digital Synthesizer(DDS) and minimizing the phase noise employing the reference clock(Ref_CLK) as the offset frequency of the Phase Locked Loop(PLL).

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.1
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• pp.73-79
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• 2020

Modern radar system requires high spectral purity and low phase noise characteristics for very low RCS target detection and high resolution SAR (Synthetic Aperture Radar) image. This paper presents a new X-band high stable frequency synthesizer for high performance radar system, which combines DAS (Direct Analog Synthesizer) and DDS (Direct Digital Synthesizer) techniques, in order to cope with very low phase noise and high frequency agility requirements. This synthesizer offers more than 10% operating bandwidth in X-band frequency and fast agile time lower than 1 usec. Also, the phase noise at 10kHz offset is lower than -136dBc/Hz, which shows an improvement of more than 10dB compared to the current state of art frequency synthesizer. This architecture can be applied to L-band and C-band application as well. This frequency synthesizer is able to used in modern AESA (Active Electronically Scanned Array) radar system and high resolution SAR application.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.192-198
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• 2007

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is stored by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). To reduce the ROM size, we use the differential quantization technique with this two ROM. First, we quantize the quarter sine wave with the $2^L$ address and store the quantized value at the Q-ROM. Second, after the $2^L$ address are equally divided into $2^M$ sampling intervals, the sampling value is quantized. And the D-ROM store only the difference between this quantized value and the Q-ROM. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is affected mostly by this ROM reduction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.